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(8)
R.SYNC
circuit
for
generation
of
VDP
hori-
zontal
and
vertical
counter
reset
pulses
in
picture
superimpose
mode
(9)
Muting
control
circuit
for
muting of
the audio
right
channel
11.
Matrix
Circuit
The
matrix
circuit
contains the following blocks.
(1)
Y, R-Y, B-Y, buffer 1
Buffer
amplifier
for
the
computer
video
outputs
Y
(luminance
signal),
R-Y,
and
B-Y
(color difference
signal)
from
the
VDP
(CPU
ass'y
TMS9129).
(2)
R, G, and
B
Matrix
Circuits
Adder
circuit
to obtain the R, G,
and
B
signals
from
the
VDP
Y,
R-Y,
and B-Y
signals.
The
R
signal
is
generated
from
the
R-Y
and
Y
signals
(R
matrix)
The
G
signal
is
generated
from
the
R-Y,
B-Y
and
Y
signals
(G
matrix)
The
B
signal
is
generated
from
the
B-Y
and
Y
signals
(B matrix)
(3)
DC
level shift circuit
The
VDP
B-Y
signal
is
subject to
a
voltage
shift
to
enable detection of picture overlay
flags in
that
signal.
12.
RGB
Generator
The
RGB
generator
consists
of
the following
blocks.
(1)
R.B.
signal
generator
The
R.B.
signal
generated
in
the matrix
circuit
is
coverted
to
the R.B.
signal
of the
digital
R.G.B
signal
by
voltage
comparator.
The R.B
adjustment
control
(VR
104)
is
made up
of
the
comparator
slice
adjustment
volume.
(2)
G.OVLYF
signal
generator
The
G
signal
generated
in
the matrix
circuit
and
the
level-shifted
B-Y
signal
are
converted
to
the
G
and
OF
(picture
overlay
flag)
signals
of the
digital
R.G.B
signal
by
voltage
compara-
tor.
13.
Composite Video
Signal
Generator
This
circuit
consists
of the
following blocks.
(1)
Buffer
3 and
buffer
4
Optimization of the
level
of
the
color subcarrier
applied to the
carrier
color
signal
modulator.
The
carrier
phase
is
inverted
in
buffer 3 to
correct
the
polarity
of the
carrier
color
signal
in
the
carrier
color
signal
modulator.
(2) Carrier
color
signal
modulator,
voltage
regula-
tor,
and
bias
circuit.
The
carrier
color
signal
is
generated
by
modula-
ting
the
VDP
R-Y and B-Y
signals
to the color
subcarrier
(4.433618MHz).
The
color subcarrier
suppression
adjustment
control
(VR106)
is
made up
of the
bias
adjustment
volume
of
the
carrier
color
signal
modulator.
And
the
voltage regulator supplies
power
for
the
carrier
color
signal
modulator
bias
circuit.
(3)
Mixing
circuit
and
carrier
color
signal
filter
The R-Y
and B-Y
carrier
color
signals
generated
in
the color
signal
modulator
are
combined by
a
mixing
circuit.
Dot
interference
is
reduced
by
restricting
the
carrier
color
signal
side
bands by
bandpass
filter.
(4)
Mixing
circuit
and
Y
buffer
2
The
VDP Y
signal
is
passed
through
Y
buffer
2
where
it
is
combined
with the
carrier
color
signal
to
form
the
composite
video
signal.
(5)
Level
shift circuit
The
level
of the
internal
video
signal
is
shifted
to
match
the
level
of the
external
video
signal.
(6)
Burst attenuator
The
burst
period
of
the
internal
video
signal
During
IC108
is
opened
while
in
computer
mode
to
attenuate the burst
signal
to
the
standard
PAL
system
burst
level.
(7)
Overlay
flag
eliminator
During
picture
superimpose
mode,
the overlay
flag
included
in
the
VDP
R-Y
and
B-Y
color
dif-
ference
signals
are
in
blank during
that
interval
to obtain
an achromatic
color difference
level.
The
white
level
adjustment
control
(VR109)
is
used
in this
level setting.
(8)
R-Y
and B-Y
buffer
2
Buffer
amplifier for
the
color difference
signal
after level
compensation
at
the
overlay
flag
eliminator.
14.
Video
Switching
Circuit
The
video switching
circuit
contains the follow-
ing
blocks.
(1)
Buffer
2 and clamp
circuit 1
The
pedestal
level
of the
external
video
signal
is
exactly
matched
with the
pedestal
level
of the
internal
video
signal.
The
video
level
adjustment
control
(VR105)
is
used
in this
level setting.
(2)
Video
switching
circuit
In
computer mode,
external
video
signal
mode,
and
picture
superimpose
mode,
the video
signal
is
switched
by
the
OVLYF
signal
(pic-
ture
superimpose
flag).
(3)
Video
amplifier
Amplification of the video switching
circuit
output
video
signal
to
lVp-p/75 ohms.
75
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