Pioneer PX-7 Service Manual page 83

PX
13. 4.
2
CAS
Decoder
Since four
16K
X
4-bit
D-RAMs
are
used
as
the
main
RAM
(consisting of
two 16K
byte
RAM
pairs
wit
h two
D-RAMs
per
pair
to
make 32K
bytes),
the
CAS
signal
from
the
gate array (IC3)
is
decoded
by SLTSLO, A14, and A15, and
is
subsequently
divided
into
CAS2
and
CAS3
generated
at
8000H
thru
BFFFH
and
COOOH
thru
FFFFH
of
slot 0.
These two
signals are
then applied to the
respective
D-RAM
pairs.
2 LINE TO 4 LINE
DECODER
13. 4.
3
Address
Multiplexer
A
14-bits address
lines
(AO
thru
A13)
are
re-
quired to
specify
16K
bytes
(2
14
)
addresses. D-
RAMs,
however,
are
only equipped
with
address
input pins for
up
to
8
bits
(AO
thru A7). Hence,
AO
thru
A13
is
divided into
row
address
(AO
thru
A7) and column
address-(A8 thru A13)
with
ad-
dressing operations being
executed
in
two
steps.
(1)
Addresses
are divided into
row and column
addresses
by
multiplexer controlled by
the
MPX
signal.
(2)
In the
DORAM,
the
row
or colu
mn
addresses
are identified
by
the
RAS
or
CAS
signal.
(3)
Column
addresses
A8
thru
A13
are
two
bits
shorter
than
row
addresses.
The
address
distrib-
ution
method
is
outlined
in
Table 13-2 below.
<Address multiplexed
Fig.
13-13 Address
multiplexer
Table 13-2 Address
distribution
Pin