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13. Printer Interface
•
8-bit
parallel
printer interface
in
conformity
with
CENTRONICS
specifications
14.
Cartridge
Slots
#1
(Front)
and
#3
(Rear)
• Connector
for
MSX
cartridge
—
input/output of
MSX
signals via
50-pin
cartridge
connector
15.
Power Supply
• +5V, +12V, and
—12V
regulated voltages
from
220/240V
AC
50/60Hz
input
• Current
limiting
of regulated outputs
to
protect
cartridge
from
destruction
by
incorrect shorting
in
a
slot
•
ANALOG
ASS'Y
A.
Video
Signal Circuits
1.
Buffer
1
Buffer
amplifier
for
external
video
signals
applied
via
the video input
terminal.
2.
External
Synchronizing
Signal
Separator
Separation of the
vertical
and
horizontal syn-
chronizing
signals
as
a
composite
synchronizing
signal
from
the
external video
signal.
3.
Internal
Synchronizing
Signal
Separator
Separation of the
vertical
and
horizontal syn-
chronizing
signals
as
a
composite
synchronizing
signal
from
the
VDP
(TMS9129)
Y
(luminance)
signal.
4.
Vertical
Synchronizing
Signal
Separator
Circuits
1
&
2
Separation of the
vertical
synchronizing
signal
from
the
composite
synchronizing
signal
separated
from
the
external video
and
VDP Y
signals.
5.
Bandpass
Filter
Extraction
of
the
chroma
signal
from
the
external
video
signal.
(The chroma
signal
is
muted
by
Q103 when
in
computer
picture
mode.)
6.
Phase
Shifter
Adjustment
of the burst phase of the
external
video
signal at
the video switching
circuit
to
match
the
computer
picture color
phase
reference.
7.
Color
Subcarrier
Generator
Circuit
The
color subcarrier generator
circuit consists
of
a quartz
resonator
PLL
circuit,
and
in
super-
impose mode,
it
is
used
to
form
a
continuous
color subcarrier
by
synchronizing with the
color
synchronizing
signal
(color burst)
in
the
external
video
signal.
The
color subcarrier
(4.433618
MHz)
is
used
as
the
carrier
(two
signals
90° out of phase
with
each
other)
for
the
carrier
color
signal
modulator.
In
computer
picture
mode,
PLL
operation
is
stopped and
the color subcarrier
frequency
becomes
the free-running frequency. This
carrier
is
also
used
as
the
reference
clock
for
the synchronizing pulse
generator.
8.
Horizontal
Synchronizing
Signal
Processing
Circuit
The
horizontal
synchronizing
signal
processing
circuit
consists
of
a
PLL
circuit
to
form
a pulse
(15.625kHz)
signal
synchronized with
the horizon-
tal
synchronizing
signal
in
the external video
signal
when
in
superimpose
mode.
This
pulse
signal
serves
as the reference
signal
for
the
VDP
clock
(10.6MHz)
generator.
The
horizontal synchroniza-
tion
adjustment
control
(VR102)
is
used
to adjust
the free-running frequency,
and
is
capable of
a
certain
degree of horizontal
position
adjustment
if
within the
PLL
circuit
lock
range.
This
pulse
signal
is
also
used
as
the
PAL
pulse for control of
the
PAL
switch
in
the color
subcarrier generator
circuit
in
both
computer and
superimpose modes.
9.
Loop
Filter
and
VCO
This
circuit
consists of
a
PLL
circuit
together
with the frequency
divider
and
phase comparator
in
the synchronizing pulse generator
which forms
part
of the
10.6MHz
VDP
clock generator
for
the
CPU
ass'y.
10.
Synchronizing
Pulse
Generator
The
synchronizing pulse generator
consists
of
the following
blocks.
(1)
Horizontal synchronizing
signal
noise suppres-
sor
(2)
External video
signal
detector
(3)
10.6MHz
PLL
generator
phase comparator
and
frequency
divider
(4)
Reference
signal
generator of
10.6MHz
PLL
generator.
(5)
Reference
signal
switching
circuit
for the
PLL
generator
and
horizontal
and
vertical
synchro-
nizing
signals
used
in
superimpose.
(6)
Counter
1
for
PAL
pulse
generation
(7)
Counter
2
for generation
of
the burst
gate
pulse
from
the
external/internal
horizontal
synchronizing
signals
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