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Gate
array
13.5
I/O
CONTROL
13.
5.
1
I/O Address
Decoder
If
th e
CPU
is
to access
a
memory
or
I/O, either
MERQ
or
IORQ
must
bec
ome
ac
tive (L).
If
an
I/O
is
accessed
by
program,
IORQ
becomes
L,
and
the
output
from
the
CPU
is
WR=L
if
the
command
is
written
in
the
I/O, or
RD=L
if
the I/O
status
is
read.
When IORQ
is
L
apart
from
during
an
Ml
cycle (that
is,
when
an I/O
request
is
generated
outside
an
interrupt
acknowledge
cycle),
the I/O
address
decoder
circuit
is
enabled
by
IOE
being
changed
to H. I/O access
signals
are
thus generated
at
8-byte
intervals
by
decoding
addresses
A3
thru
A7.
When
A7
is
H
and
A6
is
L
in
an
actual
circuit,
A3
thru
A5
is
decoded by
a 3-to-8-LINE decoder,
and
I/O access
signals
generated
at
8-
byte
intervals
from
80H
to
BFH
are allocated to
each
I/O.
As
a
result,
I/O addresses
90H
thru
97H
are allocated to
the
printer
I/F,
98H
thru
9FH
to
the
VDP,
AOH
thru
A7H
to the
PSG, and
A8H
thru
AFH
to
the
PPI.
The
I/O
map
is
outlined
in
the
table
below.
TW1
Fig.
13-14
I/O
Address decode
circuit
Table 13-3
I/O address allocation
&HA0
&HA1
&HA2
Details
Data
write
into
VRAM
Data
read
from
VRAM
Command,
address
se
Address
latch
Data
read
TMS9I29NL
equivalent
&HAB
1
&H90~"
Port
A
data
write
Port
A
data read
Port
B
data
write
Port
B
data read
Port
C
data
write
Port
C
data read
Mode
set
Strobe output
(bO)
R
Status input (bl)
I/O
addresses
from
80
to
FF
area prescribed
as
above
for
system
use.
Empty
columns
are
system
*1/0
addresses
marked
with
an
asterisk
are for
optional
equipment.
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