Pioneer PX-7 Service Manual page 57

CPU
Ass'y
(AWP-022) TP1
Thru
TP4
Functions
Description of the functions of
TP1
thru
TP4
mounted on
the
PX-7/HB,
HE
CPU
ass'y
(AWP-
022)
and
the
associated
jumper-land
JPAthru
JPD).
• Under normal
conditions, respective soldering of
JPA
thru
JPD
forms
bridge short
circuits
where
the
MSX-BASIC
ROM
and
32K
byte
RAM
become
slot
#0,
and the
front cartridge
slot
becomes
slot
#1.
•
That
is,
after the
power
is
switched
on
or
after
the
RESET
switch
is
pushed, the
CPU
is
started
up
from
slot
#0 0000H
address, resulting in the
MSX-BASIC
ROM
being
selected
and taking
control of
operations.
•
If
the
ROM, RAM,
and
internal
I/O
are
normal,
the
initial
display will
appear
on
the screen to
enable
key
inputs
under
MSX-BASIC
control.
If
an abnormal
condition
exists,
however, resulting
in
runaway
status
or
suspended
operation,
it
will
not be
possible to detect that condition
while
under
MSX-BASIC
control.
•
In
this case,
if
the inspection 2
ROM
made
ready
when
the
power was
switched on
or the
RESET
switch pushed
can be
activated
and
various
checks executed, the
location
of the abnormal
condition can be
determined.
•
In
this ass'y, slot
#0
can be
reverted to the
front
cartridge
slot
and
slot
#1
to the
MSX-BASIC
ROM
and
32K
byte
RAM
by
removing
the
sol-
der
from JPC
or JPA, and from JPB
or
JPD,
thereby enabling
activation of the inspection
2
ROM
mounted
in
the front
cartridge.
•
JPC/
JPA
and JPB/ JPD
have been
mounted on
the top
and bottom
of the
ass'y for handling
working top
the
front, or the
JPC/JPD
solder
when
working from
the bottom.
57