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13.
2.
1
CPU
(Central Processing Unit)
The
CPU
(IC1)
is
an
equivalent
Z80A
device
(LH0080A).
13.
2.
2
System Clock
The
system clock
(3.58MHz)
is
generated
by
an
oscillator
consisting
of a ceramic resonator
XI,
IC37(l/6),
and
IC8(l/6),
and
is
supplied to the
CPU, PSG,
gate
array,
and
cartridge
slots.
Fig.
13-2
System
clock
oscillator
13.
2.
3
Reset
Circuit
The
PX-7
is
initialized
by
this circuit
when
the
power
is
switched
on
or
when
the
RESET
switch
(SI)
is
switched
on.
The
CPU
is
reset
by
applying a
active-low
pulse.
When
the
power
is
switched
on, a
pulse
delayed
by
the period
of time taken
to
charge
up Cl
by
the leading edge of the
power
supply
voltage
is
applied to the
CPU.
The CPU,
PSG,
gate
array,
and
cartridge
slots
are reset
by
active-low,
and
the
PPI
and
printer
I/F are
reset
by
active-high.
RESET PULSE
GENERATED
BY
Cl
CHARGING
/
DISCHARGING.
R
I
:
CURRENT
LIMITING
0
I
:
Cl
DISCHARGED
WHEN
POWER
IS
SWITCHED
OFF.
R
I
AND R4
:
POSITIVE
FEEDBACK
RESISTANCE (SCHMITT
Fig.
13-3 Reset
circuit
13.
2.
4
WAIT
Circuit
The
WAIT
circuit inserts
a
TW
state (1
WAIT)
between
the
T2
and
T3
states in
an
Ml
cycle
(instruction fetch cycle) to
ensure
ROM
or
RAM
accessing
time
on
the
basis
of
MSX
standards.
It
is
also possible
to obtain a
WAIT
by
WAIT
request
(EXT WAIT)
from an
external source,
applying the
input
via
the
slot
section
if
necessary
from
the
external device.
Fig.
13-4
Wait
circuit
(1)
IC35
(1/2) latches
Ml
L
at
the leading edge of
the
T2
state
<p
in
the
Ml
cycle.
The
IC35(l/2)
Q
output
is
thus switched to
L.
(2)
The
CPU
reads the
L
level
applied to the
WAIT
pin
from
the IC35(l/2)
Q
output
at
the
trailing
edge of the
T2
state
0,
and
subsequently
generates the
TW
state.
(3)
At
the leading
edge of the
TW
state
<t>,
IC35
(2/2) latches
the IC35(l/2)
Q
output
L
level
by
the
D
input, resulting
in
an
L
level
output from
IC35(2/2) Q.
(4)
IC35(l/2)
is
preset
by
IC35(2/2)
Q
output
L
level,
and
the IC35(l/2)
Q
output
(to
WAIT)
is
switched
to
H
level.
(5)
At
the leading
edge of
the
T3
state
<t>,
IC35
(2/2) latches
the IC35(l/2)
Q
output
H
level,
resulting in
an
H
level
output
from
IC35(2/2)
Q.
The
TW
state
is
thus
inserted.
(6)
When
the
slot
section
EXT WAIT
then
becomes
L, the
IC40 output
is
switched to L,
resulting
in
the IC35(l/2)
CL
and
IC35(2/2)
PR
inputs
also
becoming
L
and
the
IC3
5(2/2)
Q
output
becoming
H. Therefore, an
L
level
output
is
obtained
from IC35(l
/2)
Q, and an
L
level
input
is
applied to the
WAIT
pi
n
of the
CPU.
The
L
output
appli
ed
to
this
WAIT
pin
is
maintained
until
the
EXT WAIT
status
(switch
to
H)
is
cancelled
(irrespective
of 0
and
Ml).
70
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