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13.
18
Horizontal
Synchronizing
Signal Processing
Circuit
(see
Fig.
13-54)
The
horizontal synchronizing
signal
processing
circuit
generates
a
15.625kHz
horizontal synchro-
nizing
signal
frequency synchronized with the
external video
signal
and
VDP Y
signal
(luminance
signal)
on
the
basis
of
the horizontal synchronizing
signal
separated
from
those
signals.
IC103
forms
a
PLL
oscillator
which
oscillates at
the
free-running
frequency
when
there
is
no
input
applied.
Although
this
free-running
frequency can
be
adjusted
by
VR102,
the
PLL
will
not lock
if
the
frequency
is
too
far
away
from 15.625kHz.
The
horizontal position
can be
adjusted to a
small degree
by
VR102
within
the range
where
the
PLL
is
locked
(see
Photo.
13-22).
The Cl
50 and
C151
mylar
capacitors are
used
for
temperature
compensation
for
the
ocillating
frequency
(see
Photo.
13-22).
13.
19
Loop
Filter
and
VCO
(see
Fig.
13-55)
This loop
filter
and
VCO
(voltage controlled
oscillator)
form
a
PLL
oscillator
with the phase
comparator and counter
gate array
(synchronizing
pulse generator)
IC102.
A
10.6MHz
clock for the
VDP
(TMS9129)
is
generated.
The
error voltage
from
the
gate array
phase
comparator (comparison frequency
of
3.90625kHz
in
synthesis
mode
and 3.903kHz
in
computer
mode)
is
passed to the
Q111/Q112
loop
filter.
The
filter
output
is
then
applied to
the
D101
variable
capacitance
diode
to control
the
VCO.
The
VCO
oscillates
on
the
basis
of
the
4.
433618MHz
color
subcarrier
signal
during
computer mode, and
on
the
basis
of the frequency of the
horizontal syn-
chronizing
signal in
the
external
video
signal
when
in
external
video
mode,
the
oscillating
frequency
being locked
at
frequencies
determined
by
the
following
equations:—
•
When
in
computer
mode
fcLK
= 4
.433618MHz
(color subcarrier frequen-
cy) /1
136
x 4 x
684
= 10.6781
5039MHz
•
When
in
video
picture synthesis
mode
fcLK
= 15.625kHz
(external
video
horizontal
synchronizing
signal
frequency) x
684
=
10.687500MHz
A DC
bias
is
applied to the gate array
via
R154
and
R153
to
ensure
that the
oscillator
output
is
applied
within
the
0
to
5V
range.
The
D134
diode
protects
the
gate array
from
inputs
in
excess
of
5V
(see
Photo.
13-23).
a:
External video input {horizontal synchronizing
signal)
b:
External
composite
synchronizing
signal
input
(IC102
pin 7
EXSI)
5V/div.
c:
Waveform
©
EXHP1
5V/div.
d:
Waveform
©
FH
5V/div.
Photo. 13-22
Video input/EXSI/EXHPI/FH
timing
(picture synthesis
mode)
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