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3 Name and Function of Each Part
3 Name and Function of Each Part
The following shows the name of each part of the S5U1C17001H.
3.1 Left Side Panel
4-pin Flash programming power supply connector (white)
GND pin
4-pin target interface connector (black)
This connector is used to input/output the debug signals (DCLK, DSIO, and DST2) from/to the S1C processor
on the target system. See Section 4.1.1, "Target Interface Connector," for the pin assignment and connection.
4-pin Flash programming power supply connector (white)
This connector is used to output the reset signal to the target system and to supply a power voltage for Flash
programming
(Note)
. Also it is used to input the target operating voltage when the target system voltage level is
used for the debug signal interface. See Section 4.1.2, "Flash Programming Power Supply Connector," for the
pin assignment and connection.
Note: The S5U1C17001H is equipped with a 7-V Flash programming power supply with output
capacities of 30mA. Note, however, that its usage depends on the S1C processor. Be sure to
avoid using this power supply for the S1C processor (do not set SW8 of the DIP switch to ON) if
its technical manual does not describe the usage of the Flash programming power supply, as the
chip may be destroyed due to overvoltage. This pin must be left open if the connector is attached
on the target system.
DIP switch
The DIP switch assembly is used to select the target CPU core, Flash programmer mode, DSIO signal level,
connection test feature, firmware update feature, and Flash programming voltage output.
Note: The changed switch settings will take effect after the RESET/START switch is pressed.
Selecting the target CPU core (SW1)
SW1
OPEN (h)
ON (i)
4
BRK IN pin
DIP switch
Left Side Panel
1
2
3
4
5
6
Figure 3.1.1 DIP Switch Assembly
Table 3.1.1 SW1 Settings
S1C17 Core (default)
S1C33 Core *
Seiko Epson Corporation
4-pin target interface connector (black)
OPEN
7
8
ON
Setting
* Scheduled to be supported with a firmware update
S5U1C17001H USER MANUAL
(ICDMINI VER1.0 and VER1.1)
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