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E P I C B o a r d
E P I C - 9 4 5 7 R e v . B
A.1 Programming
EPIC-9457 Rev.B utilizes ITE 8781 chipset as its
watchdog timer controller. Below are the procedures to complete
its configuration and the AAEON initial watchdog timer
program is also attached based on which you can
develop customized program to fit your application.
Configuring Sequence Description
After the hardware reset or power-on reset, the ITE 8781 enters the
normal mode with all logical devices disabled except
KBC. The initial state (enable bit ) of this logical device (KBC) is
determined by the state of pin 121 (DTR1#) at the falling edge of
the system reset during power-on reset.
Appendix A Programming the Watchdog Timer A-2
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