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Aaeon EMB-QM87A User Manual

Intel 4th generation coretm i7/i5/ celeron processor mini-itx gigabit ethernet 4 usb2.0, 6 usb3.0, 6 com 4 sata 6.0gb/s, 2 sata 3.0 gb/s support raid 0,1,5,10 1 pci-e[x16], 1 mini-pcie socket, 1 optional tpm
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M i n i - I T X
E M B - Q M 8 7 A
EMB-QM87A
®
TM
Intel
4th Generation Core
i7/i5/ Celeron Processor
Mini-ITX
Gigabit Ethernet
4 USB2.0, 6 USB3.0, 6 COM
4 SATA 6.0Gb/s, 2 SATA 3.0 Gb/s
Support RAID 0,1,5,10
1 PCI-E[x16], 1 Mini-PCIe socket, 1 Optional TPM
st
EMB-QM87A Manual 1
Ed.
th
February 10
, 2014

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  • Page 1 4th Generation Core i7/i5/ Celeron Processor Mini-ITX Gigabit Ethernet 4 USB2.0, 6 USB3.0, 6 COM 4 SATA 6.0Gb/s, 2 SATA 3.0 Gb/s Support RAID 0,1,5,10 1 PCI-E[x16], 1 Mini-PCIe socket, 1 Optional TPM EMB-QM87A Manual 1 February 10 , 2014...
  • Page 2 AAEON assumes no liabilities resulting from errors or omissions in this document, or from the use of the information contained herein. AAEON reserves the right to make changes in the product design without notice to its users.
  • Page 3 M i n i - I T X E M B - Q M 8 7 A Acknowledgments All other products’ name or trademarks are properties of their respective owners. AMI is a trademark of American Megatrends Inc. CompactFlash is a trademark of the Compact Flash ™...
  • Page 4 Before you begin installing your card, please make sure that the following materials have been shipped: Jumper Cap SATA Cable 7P SATA PWR Cable 4P Back I/O Shield Product DVD-ROM EMB-QM87A If any of these items should be missing or damaged, please contact your distributor or sales representative immediately.

  • Page 5: Table Of Contents

    M i n i - I T X E M B - Q M 8 7 A Contents Chapter 1 General Information 1.1 Introduction..............1-2 1.2 Features ..............1-4 1.3 Specifications ............1-5 Chapter 2 Quick Installation Guide 2.1 Safety Precautions ............ 2-2 2.2 Location of Connectors and Jumpers .......
  • Page 6 M i n i - I T X E M B - Q M 8 7 A 2.17 COM Port Box Header (COM2~6) ......2-14 2.18 Digital I/O Pin Header (DIO1)........ 2-15 2.27 SATA Power Wafer (CN3,CN10) ......2-15 2.22 4 PIN Fan Wafer (CN9,CN6)......... 2-16 2.23 8 pin DC-IN Power Connector Power (CN22)..
  • Page 7 M i n i - I T X E M B - Q M 8 7 A Appendix C Mating Connector C.1 List of Mating Connectors and Cables....C-2 Appendix D Electrical Specifications for I/O Ports D.1 DIO Programming..........D-2 D.2 Digital I/O Register..........

  • Page 8: Chapter 1 General Information

    M i n i - I T X E M B - Q M 8 7 A Chapter General Information 1- 1 Chapter 1 General Information...

  • Page 9: Introduction

    Generation Intel® Core™ i7 / i5 / Celeron® integrated graphics engine (Gen 8, DX11.1, OpenGL 3.2, OpenCL 1.2) to offer high definition display function. With all of its integrated features, the EMB-QM87A strikes a balance of performance and price. This versatile product targets Industrial Automation, Entertainment, Networking, KIOSK/POS,...
  • Page 10 M i n i - I T X E M B - Q M 8 7 A applications that require high performance and high reliability. Chapter 1 General Information...

  • Page 11: Features

    M i n i - I T X E M B - Q M 8 7 A 1.2 Features ® Socket BGA 1364, Intel Generation Core™ i7/i5/Celeron Processor ® Intel Generation Core™ i7/i5/Celeron + QM87 204-pin Dual-channel DDR3L 1333/1600 MHz SODIMM x 2, Up to 16 GB Gigabit Ethernet x 2 Dual Display Version: Dual 24-bit LVDS, VGA, HDMI...

  • Page 12: Specifications

    M i n i - I T X E M B - Q M 8 7 A 1.3 Specifications System From Factor Mini-ITX Processor Socket BGA 1364, Intel® 4th Generation Core™ i7/i5 Processor System Memory 204-pin Dual-channel DDR3L 1333/1600 MHz SODIMM x 2, Up to 16 GB ®...
  • Page 13 M i n i - I T X E M B - Q M 8 7 A Board Size 6.7" x 6.7" (170mm x 170mm) Gross Weight 1.32 lb (0.6Kg) Operating Temperature 32°F~140°F (0°C~60°C) Storage Temperature -4°F~158°F (-20°C~70°C) Operating Humidity 5% ~ 90% relative humidity, non-condensing Display: Supports CRT/LCD simultaneous / dual / triple...
  • Page 14 M i n i - I T X E M B - Q M 8 7 A 5/12V/RING by jumper on pin-9 USB3.0 x 6 USB2.0 x 4 PS/2 Port Keyboard x 1, Mouse x 1 Digital I/O 8-bit programmable (4-in / 4-out) Audio Line-in, Mic-in, Line-out Chapter 1 General Information...

  • Page 15: Chapter 2 Quick Installation Guide

    M i n i - I T X E M B - Q M 8 7 A Chapter Quick Installation Guide 2 - 1 Chapter 2 Quick Installation Guide...

  • Page 16: Safety Precautions

    M i n i - I T X E M B - Q M 8 7 A 2.1 Safety Precautions Always completely disconnect the power cord from your board whenever you are working on it. Do not make connections while the power is on, because a sudden rush of power can damage sensitive electronic components.

  • Page 17: Location Of Connectors And Jumpers

    M i n i - I T X E M B - Q M 8 7 A 2.2 Location of Connectors and Jumpers Component Side 2 - 3 Chapter 2 Quick Installation Guide...
  • Page 18 M i n i - I T X E M B - Q M 8 7 A Solder Side 2 - 4 Chapter 2 Quick Installation Guide...

  • Page 19: Mechanical Drawing

    M i n i - I T X E M B - Q M 8 7 A 2.3 Mechanical Drawing Component Side 2 - 5 Chapter 2 Quick Installation Guide...
  • Page 20 M i n i - I T X E M B - Q M 8 7 A Solder Side 2 - 6 Chapter 2 Quick Installation Guide...

  • Page 21: List Of Jumpers

    M i n i - I T X E M B - Q M 8 7 A 2.4 List of Jumpers The board has a number of jumpers that allow you to configure your system to suit your application. The table below shows the function of each of the board's jumpers: Label Function CN12...
  • Page 22 M i n i - I T X E M B - Q M 8 7 A CN3,CN10 SATA POWER Wafer 4 Pin System Fan Connector 4 Pin CPU Fan Connector CN11 SPI Programming Connector CN14 USB3.0 Port BOX Header CN18 Debug Port Connector CN21...

  • Page 23: Setting Jumpers

    M i n i - I T X E M B - Q M 8 7 A 2.6 Setting Jumpers You configure your card to match the needs of your application by setting jumpers. A jumper is the simplest kind of electric switch. It consists of two metal pins and a small metal clip (often protected by a plastic cover) that slides over the pins to connect them.

  • Page 24: At/Atx Select (Cn13)

    M i n i - I T X E M B - Q M 8 7 A 2.7 AT/ATX Select (CN13) CN13 Function ATX (Default) 2.8 Clear ME (CN16) CN16 Function Normal (Default) Clear CMOS 2.9 Clear PCH CMOS (CN17) CN17 Function Normal (Default)

  • Page 25: Ddr3L Voltage Select (Jp1)

    M i n i - I T X E M B - Q M 8 7 A +5V (Default) +12V LVDS Backlight Brightness Control CN20 Function 8-10 Voltage Mode (Default) 10-12 PWM Mode 2.11 DDR3L Voltage Select (JP1) CN13 Function 1.35V (Default) 1.5V 2.12 COM1 Ring/+5V/+12V Select (JP2)

  • Page 26: Vga Port Connector (Vga1)

    M i n i - I T X E M B - Q M 8 7 A SPEAKER(-) SPEAKER(+) Power LED (-) Power LED (+) Reset Switch (-) Reset Switch (+) Note: The max. rating of pin1,2,3,4,7,8 is 0.25A @ 5V 2.14 VGA Port Connector (VGA1) Signal Signal...

  • Page 27: Com Port Connector (Com1)

    M i n i - I T X E M B - Q M 8 7 A Signal Signal DATA2_P N.C. DATA2_N DATA1_P DATA0_P DATA1_N DATA0_N CLK_P N.C. CLK_N DDC_CLK N.C. DDC_DATA 2.16 COM Port Connector (COM1) RS-232 Signal Signal DCD1 RXD1 TXD1...

  • Page 28: Com Port Box Header (Com2~6)

    M i n i - I T X E M B - Q M 8 7 A RTS1 CTS1 RI1/5V/12V RS-422 Signal Signal RS422_TX- RS422_RX+ RS422_TX+ RS422_RX- NC/5V/12V RS-485 Signal Signal RS485_D- RS485_D+ NC/5V/12V Note: The max. rating of pin9 is 1A @ 5V & 12V 2.17 COM Port Box Header (COM2~6) Signal Signal...

  • Page 29: Digital I/O Pin Header (Dio1)

    M i n i - I T X E M B - Q M 8 7 A Note: The max. rating of pin9 is 1A @ 5V & 12V 2.18 Digital I/O Pin Header (DIO1) Signal Signal OUT0 OUT1 OUT2 OUT3 +3.3V Note: The max.

  • Page 30: Pin Fan Wafer (Cn9,Cn6)

    M i n i - I T X E M B - Q M 8 7 A The max. rating of pin5 is 1 A @ 5V 2.22 4 PIN Fan Wafer (CN9,CN6) Signal Signal +12V FAN_TAC FAN_CTL Note: The max. rating of pin2 is 1A @ 12V 2.23 8 pin DC-IN Power Connector Power (CN22) Signal Signal...

  • Page 31: Ps/2 Keyboard & Mouse Connector (Cn25)

    M i n i - I T X E M B - Q M 8 7 A Signal Signal +5V_USB P1_SSRX- P1_SSRX+ P1_SSTX- P1_SSTX+ P1_D- P1_D+ N.C. P2_D+ P2_D- P2_SSTX+ P2_SSTX- P2_SSRX+ P2_SSRX- +5V_USB N.C. Note: The max. rating of pin1 is 0.9A @ 5V The max.

  • Page 32: Usb Connector (Usb1,Usb2)

    M i n i - I T X E M B - Q M 8 7 A +5V_KB KB_CLK N.C. MS_DATA N.C. +5V_KB MS_CLK N.C. Note: The max. rating of pin4 is 0.275A @ 5V The max. rating of pin10 is 0.275A @ 5V 2.20 USB Connector (USB1,USB2) Signal Signal...

  • Page 33: Lvds Connector (Lvds1)

    M i n i - I T X E M B - Q M 8 7 A Signal Signal SATA_TXP SATA_TXN SATA_RXN SATA_RXP 2.25 LVDS Connector (LVDS1) Signal Signal BKLT_EN BKLT_CTRL LVDSVCC LVDS1_CLK# LVDS1_CLK LVDSVCC LVDS1_DATA0# LVDS1_DATA0 LVDS1_DATA1# LVDS1_DATA1 LVDS1_DATA2# LVDS1_DATA2 LVDS1_DATA3# LVDS1_DATA3...

  • Page 34: Lvds Inverter Power Wafer (Cn21)

    M i n i - I T X E M B - Q M 8 7 A LVDS2_DATA3# LVDS2_DATA3 LVDSVCC LVDS2_CLK# LVDS2_CLK Note: The max. rating of pin3,7 is 2A @ 5V / 3.3V 2.26 LVDS Inverter Power Wafer (CN21) Signal Signal 12V / 5V...
  • Page 35 M i n i - I T X E M B - Q M 8 7 A Below Table for China RoHS Requirements 产品中有毒有害物质或元素名称及含量 AAEON Main Board/ Daughter Board/ Backplane 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯醚 (Pb) (Hg)
  • Page 36 M i n i - I T X E M B - Q M 8 7 A 2 - 22 Chapter 2 Quick Installation Guide...
  • Page 37 E M B - Q M 8 7 A Chapter BIOS Setup Chapter 3 AMI BIOS Setup 3-1...

  • Page 38: System Test And Initialization

    4. The CMOS memory has lost power and the configuration information has been erased. The EMB-QM87A CMOS memory has an integral lithium battery backup for data retention. You will need to replace the battery when Chapter 3 AMI BIOS Setup 3-2...

  • Page 39: Ami Bios Setup

    E M B - Q M 8 7 A it finally runs down. 3.2 AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This type of information is stored in battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off.
  • Page 40 E M B - Q M 8 7 A Setup Menu Setup submenu: Main Chapter 3 AMI BIOS Setup 3-4...
  • Page 41 E M B - Q M 8 7 A Setup submenu: Advanced Chapter 3 AMI BIOS Setup 3-5...
  • Page 42 E M B - Q M 8 7 A Super IO Configuration Chapter 3 AMI BIOS Setup 3-6...
  • Page 43 E M B - Q M 8 7 A Serial Port 1 Configuration Options summary: Serial Port Disabled Enabled Enable or Disable Serial Port (COM) Device Mode RS232 RS422 RS485 Select working model Serial Port Auto IO=3F8h; IRQ=4; IO=3F8h; IRQ=3,4 IO=2F8h;...
  • Page 44 E M B - Q M 8 7 A Serial Port 2 Configuration Options summary: Serial Port Disabled Enabled Enable or Disable Serial Port (COM) Serial Port Auto IO=2F8h; IRQ=3; IO=3F8h; IRQ=3,4 IO=2F8h; IRQ=3,4 IO=3E8h; IRQ=3,4 IO=2E8h; IRQ=3,4 Select an optimal setting for Super IO device. Chapter 3 AMI BIOS Setup 3-8...
  • Page 45 E M B - Q M 8 7 A Serial Port 3 Configuration Options summary: Serial Port Disabled Enabled Enable or Disable Serial Port (COM) Serial Port Auto IO=3E8h; IRQ=10, IO=3E8h; IRQ=10, IO=2E8h; IRQ=10, IO=2D0h; IRQ=10, IO=2C0h; IRQ=10, Select an optimal setting for Super IO device. Chapter 3 AMI BIOS Setup 3-9...
  • Page 46 E M B - Q M 8 7 A Serial Port 4 Configuration Options summary: Serial Port Disabled Enabled Enable or Disable Serial Port (COM) Serial Port Auto IO=2E8h; IRQ=10, IO=3E8h; IRQ=10, IO=2E8h; IRQ=10, IO=2D0h; IRQ=10, IO=2C0h; IRQ=10, Select an optimal setting for Super IO device. Chapter 3 AMI BIOS Setup 3-10...
  • Page 47 E M B - Q M 8 7 A Serial Port 5 Configuration Options summary: Serial Port Disabled Enabled Enable or Disable Serial Port (COM) Serial Port Auto IO=2D0h; IRQ=10, IO=3E8h; IRQ=10, IO=2E8h; IRQ=10, IO=2D0h; IRQ=10, IO=2C0h; IRQ=10, Select an optimal setting for Super IO device. Chapter 3 AMI BIOS Setup 3-11...
  • Page 48 E M B - Q M 8 7 A Serial Port 6 Configuration Options summary: Serial Port Disabled Enabled Enable or Disable Serial Port (COM) Serial Port Auto IO=2C0h; IRQ=10, IO=3E8h; IRQ=10, IO=2E8h; IRQ=10, IO=2D0h; IRQ=10, IO=2C0h; IRQ=10, Select an optimal setting for Super IO device. Chapter 3 AMI BIOS Setup 3-12...
  • Page 49 E M B - Q M 8 7 A H/W Monitor Chapter 3 AMI BIOS Setup 3-13...
  • Page 50 E M B - Q M 8 7 A Smart Fan Function Options summary: Fan 1,2 Smart Fan Mode Manual RPM Mode Manual Duty Mode Auto RPM Mode Auto Duty-Cycle Mode Smart Fan Mode Select Fan off temperature limit 15 (0-127) Fan will of when temperature lower than this limit.
  • Page 51 E M B - Q M 8 7 A PWM SLOPE SETTING 0.125 PWM 0.25 PWM 0.5 PWM 1 PWM 2 PWM 4 PWM 8 PWM 15.875 PWM PWM SLOPE Selection Chapter 3 AMI BIOS Setup 3-15...
  • Page 52 E M B - Q M 8 7 A Serial Port Cons Options summary: Console Redirection Disabled Enabled Console Redirection Enabled or Disabled. Chapter 3 AMI BIOS Setup 3-16...
  • Page 53 E M B - Q M 8 7 A Console Redirection Settings Options summary: Terminal Type VT100 VT100+ VT-UTF8 ANSI Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or more bytes.
  • Page 54 E M B - Q M 8 7 A Parity None Even Mark Space A parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1’s in the data bits is even. Odd: parity bit is 0 if num of 1’s in the data bits is odd.
  • Page 55 E M B - Q M 8 7 A VT-UTF8 Combo Key Support Disabled Enabled Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals Recorder Mode Disabled Enabled On this mode enabled only text will be send. This is to capture Terminal data. Resolution 100x31 Disabled Enabled...
  • Page 56 E M B - Q M 8 7 A Power Management Options summary: Power Mode ATX Type AT Type Select Power Supply Mode. ACPI Sleep State Suspend Disabled S3 only (Suspend to RAM) Select ACPI sleep state the system will enter when the SUSPEND button is pressed.
  • Page 57 E M B - Q M 8 7 A Enabled Enable or disable System wake on alarm event. When enable, System will wake on the hr::min::sec specified. Wake up day Select 0 for daily system wake up, 1-31 for which day of month that you would like the system to wake up.
  • Page 58 E M B - Q M 8 7 A CPU Configuration Chapter 3 AMI BIOS Setup 3-22...
  • Page 59 E M B - Q M 8 7 A Options summary : Hyper-threading Disabled Enabled Enabled for Windows XP and Linux (OS optimized for Hyper-Threading Technology) and Disabled for other OS (OS not optimized for Hyper-Threading Technology). When Disabled only on thread per enabled core is enabled. Intel Virtualization Technology Disabled Enabled...
  • Page 60 E M B - Q M 8 7 A AMT Configuration Options summary: Intel AMT Disabled Enabled Enable/Disable Intel ® Active Management Technology BIOS Extension. Note : iAMT H/W is always enabled. This option just controls the BIOS extension execution. If enabled, this requires additional firmware in the SPI device Un-Configure ME Disabled...
  • Page 61 E M B - Q M 8 7 A SATA Configuration (IDE) Options summary : SATA Controller(s) Disabled Enabled Enable or disable SATA Device. SATA Mode Selection AHCI RAID Determines how SATA controller(s) operate. Chapter 3 AMI BIOS Setup 3-25...
  • Page 62 E M B - Q M 8 7 A SATA Configuration (AHCI) Options summary : SATA Controller Speed Disabled Enabled Enable or disable SATA Device. SATA Mode Selection Default Gen1 Gen2 Gen3 Indicates the maximum speed the SATA controller can support. Port Disabled Enabled...
  • Page 63 E M B - Q M 8 7 A SATA Device Type Hard Disk Drive Solid State Drive Indentify the SATA port is connected to Solid State Drive or Hard Disk Drive. Spin Up Device Disabled Enabled On an edge detect from 0 to 1, the PCH starts a COMRESET initialization sequence to device.
  • Page 64 E M B - Q M 8 7 A SATA Configuration (RAID) Options summary : SATA Controller Speed Disabled Enabled Enable or disable SATA Device. SATA Mode Selection Default Gen1 Gen2 Gen3 Indicates the maximum speed the SATA controller can support. Port Disabled Enabled...
  • Page 65 E M B - Q M 8 7 A SATA Device Type Hard Disk Drive Solid State Drive Indentify the SATA port is connected to Solid State Drive or Hard Disk Drive. Spin Up Device Disabled Enabled On an edge detect from 0 to 1, the PCH starts a COMRESET initialization sequence to device.
  • Page 66 E M B - Q M 8 7 A USB Configuration Options summary: Legacy USB Support Enabled Disabled Auto Enables Legacy USB support. AUTO option disables legacy support if no USB devices are connected. DISABLE option will keep USB device available only for EFI applications.
  • Page 67 E M B - Q M 8 7 A Dynamic Digital IO Options Summary: DIOx Direction Input (DIO0,1,2,3) Output (DIO4,5,6,7) Set Digital IO as Input or Output Output Level Set Digital IO Output as Hi or Low Chapter 3 AMI BIOS Setup 3-31...
  • Page 68 E M B - Q M 8 7 A Setup submenu: Chipset Chapter 3 AMI BIOS Setup 3-32...
  • Page 69 E M B - Q M 8 7 A PCH-IO Configuration Options summary: PCH LAN Controller Enabled Disabled Enable or disable onboard NIC. LAN RTL8111E Disabled Enabled Control the PCI Express Root Port. Mini Card Disabled Enabled Control the PCI Express Root Port. Aazlia Disabled Enabled...
  • Page 70 E M B - Q M 8 7 A System Agent (SA) Configuration Options summary : VT-d Disabled Enabled Check to enable VT-d function on MCH. Primary Display Auto IGFX PCIE Select which of IGFX/PEG/PCI Graphic device should be Primary Display. Internal Graphics Auto Disabled...
  • Page 71 E M B - Q M 8 7 A Select the Video Device which will be activated during POST. This has no effect if external graphics present. Secondary boot display selection will appear based on your selection. VGA modes will be supported only on primary display. Secondary IGFX Boot Display Disabled LVDS...
  • Page 72 E M B - Q M 8 7 A Memory Configuration Chapter 3 AMI BIOS Setup 3-36...
  • Page 73 E M B - Q M 8 7 A Boot Options summary : Quite Boot Disabled Enabled Enables or disables Quiet Boot option. Launch I218LM PXE OpROM Disabled Enabled Enabled or Disable Legacy Boot Option for I218LM. Launch RTL8111E PXE OpROM Disabled Enabled Enabled or Disable Legacy Boot Option for RTL8111E.
  • Page 74 E M B - Q M 8 7 A Security Change User/Supervisor Password You can install a Supervisor password, and if you install a supervisor password, you can then install a user password. A user password does not provide access to many of the features in the Setup utility. If you highlight these items and press Enter, a dialog box appears which lets you enter a password.
  • Page 75 E M B - Q M 8 7 A Setup submenu: Exit Chapter 3 AMI BIOS Setup 3-39...

  • Page 76: Chapter 4 Driver Installation

    M i n i - I T X E M B - Q M 8 7 A Chapter Driver Installation 4 -1 Chapter 4 Driver Installation...
  • Page 77 M i n i - I T X E M B - Q M 8 7 A The EMB-QM87A comes with an AutoRun DVD-ROM that contains all drivers and utilities that can help you to install the driver automatically. Insert the driver DVD, the driver DVD-title will auto start and show the installation guide.
  • Page 78 M i n i - I T X E M B - Q M 8 7 A 4.1 Installation: Insert the EMB-QM87A DVD-ROM into the DVD-ROM drive. And install the drivers from Step 1 to Step 9 in order. Step 1 – Install Chipset Driver 1.
  • Page 79 M i n i - I T X E M B - Q M 8 7 A Step 4 – Install Audio Driver 1. Click on the Step 4- Audio folder and select the OS folder your system is 2. Double click on the .exe located in each OS folder 3.
  • Page 80 M i n i - I T X E M B - Q M 8 7 A Step 8 – Install TPM Driver 4. Click on the STEP8-TPM folder and select the OS folder your system is 5. Double click on the Setup.exe file 6.
  • Page 81 M i n i - I T X E M B - Q M 8 7 A Step 9 – Install UART Driver (Optional) ® For Windows 1. Click on the STEP9-UART folder and double click on patch.bat file 2. Follow the instructions that the window shows 3.
  • Page 82 M i n i - I T X E M B - Q M 8 7 A 2. Change User Account Control Settings to [Never notify] 3. Reboot and Administrator login. 4 -7 Chapter 4 Driver Installation...
  • Page 83 M i n i - I T X E M B - Q M 8 7 A 4. To run patch.bat with [Run as administrator]. 4 -8 Chapter 4 Driver Installation...
  • Page 84 M i n i - I T X E M B - Q M 8 7 A ® For Windows 1. Right click [Command Prompt] and [run as administrator] 2. Run Command Prompt by administrator. 4 -9 Chapter 4 Driver Installation...
  • Page 85 M i n i - I T X E M B - Q M 8 7 A 3. Run patch.bat in UART driver folder path. 4. Update successful. 4 -10 Chapter 4 Driver Installation...
  • Page 86 M i n i - I T X E M B - Q M 8 7 A 5. Restart. 6. Com port driver\serial.sys, provider will change to [Windows(R) Win7 DDK provider]. 4 -11 Chapter 4 Driver Installation...

  • Page 87: Appendix A Programming The Watchdog Timer

    M i n i - I T X E M B - Q M 8 7 A Appendix Programming the Watchdog Timer Appendix A Programming the Watchdog Timer A-1...

  • Page 88: Watchdog Timer Initial Program

    M i n i - I T X E M B - Q M 8 7 A A.1 Watchdog Timer Initial Program Table 1 : SuperIO relative register table   Default Value Note  SIO MB PnP Mode Index Register  Index  0x2E   (Note1) 0x2E or 0x4E  SIO MB PnP Mode Data Register  Data  0x2F   (Note2) 0x2F or 0x4F  Table 2 : Watchdog relative register table    LDN ...
  • Page 89 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ // SuperIO relative definition (Please reference to Table 1)  #define byte    SIOIndex    //This parameter is represented from Note1  #define byte    SIOData    //This parameter is represented from Note2  #define    void    IOWriteByte(byte IOPort, byte Value);  #define    byte    IOReadByte(byte IOPort);  // Watch Dog relative definition (Please reference to Table 2)  #define byte ...
  • Page 90 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************  Main VOID    (){    // Procedure : AaeonWDTConfig    // (byte)Timer : Time of WDT timer.(0x00~0xFF)    // (boolean)Unit : Select time unit(0: second, 1: minute).    AaeonWDTConfig();      // Procedure : AaeonWDTEnable  // This procudure will enable the WDT counting.    AaeonWDTEnable();  }  ************************************************************************************ Appendix A Programming the Watchdog Timer A-6...
  • Page 91 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ // Procedure : AaeonWDTEnable  AaeonWDTEnable () VOID    {  WDTEnableDisable( );  EnableLDN, EnableReg, EnableBit, 1 }    // Procedure : AaeonWDTConfig  AaeonWDTConfig () VOID    {  // Disable WDT counting  WDTEnableDisable( );  EnableLDN, EnableReg, EnableBit, 0 // Clear Watchdog Timeout Status  WDTClearTimeoutStatus();  // WDT relative parameter setting  WDTParameterSetting(); ...
  • Page 92 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ SIOEnterMBPnPMode() VOID    {    IOWriteByte(SIOIndex, 0x87);    IOWriteByte(SIOIndex, 0x87);  }    SIOExitMBPnPMode() VOID    {    IOWriteByte(SIOIndex, 0xAA);  }    SIOSelectLDN(byte LDN) VOID    {  IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 ...

  • Page 93: Appendix B I/O Information

    M i n i - I T X E M B - Q M 8 7 A Appendix I/O Information Appendix B I/O Information...

  • Page 94: I/O Address Map

    M i n i - I T X E M B - Q M 8 7 A B.1 I/O Address Map Appendix B I/O Information...
  • Page 95 M i n i - I T X E M B - Q M 8 7 A Appendix B I/O Information...

  • Page 96: Memory Address Map

    M i n i - I T X E M B - Q M 8 7 A B.2 Memory Address Map Appendix B I/O Information...

  • Page 97: Irq Mapping Chart

    M i n i - I T X E M B - Q M 8 7 A B.3 IRQ Mapping Chart Appendix B I/O Information...
  • Page 98 M i n i - I T X E M B - Q M 8 7 A Appendix B I/O Information...
  • Page 99 M i n i - I T X E M B - Q M 8 7 A Appendix B I/O Information...
  • Page 100 M i n i - I T X E M B - Q M 8 7 A Appendix B I/O Information...

  • Page 101: Dma Channel Assignments

    M i n i - I T X E M B - Q M 8 7 A B.4 DMA Channel Assignments Appendix B I/O Information...

  • Page 102: Appendix C Mating Connector

    M i n i - I T X E M B - Q M 8 7 A Appendix Mating Connector C - 1 Appendix C Mating Connector...

  • Page 103: List Of Mating Connectors And Cables

    M i n i - I T X E M B - Q M 8 7 A C.1 List of Mating Connectors and Cables The table notes mating connectors and available cables. Mating Connector Connector Available Cable Function Label Cable Vendor Model No.
  • Page 104 PINREX 770-83-07SG29 SATA4. Connector CABLE USB2.0 USB1, USB2 PINREX 222-97-05GBE1 pin header USB3.0 CN14 PINREX 52X-40-20GV52 pin header Note: The AAEON Cable P/N with “ * ” sign is for WiTAS series products. C - 3 Appendix C Mating Connector...

  • Page 105: Appendix D Electrical Specifications For I/O Ports

    M i n i - I T X E M B - Q M 8 7 A A ppendix Electrical Specifications for I/O Ports Appendix E Electrical Specifications for I/O Ports...

  • Page 106: Dio Programming

    M i n i - I T X E M B - Q M 8 7 A D.1 DIO Programming EMB-QM87A utilizes FINTEK 81866 chipset as its Digital I/O controller. Below are the procedures to complete its configuration and the AAEON initial watchdog timer program is also attached based on which you can develop customized program to fit your application.

  • Page 107: Digital I/O Register

    M i n i - I T X E M B - Q M 8 7 A D.2 Digital I/O Register Table 1 : SuperIO relative register table    Default Value Note  SIO MB PnP Mode Index Register  Index  0x2E   (Note1) 0x2E or 0x4E  SIO MB PnP Mode Data Register  Data  0x2F   (Note2) 0x2F or 0x4F  Table 2 : Digital Input relative register table  LDN  Register  BitNum ...

  • Page 108: Digital I/O Sample Program

    M i n i - I T X E M B - Q M 8 7 A D.3 Digital I/O Sample Program ************************************************************************************ // SuperIO relative definition (Please reference to Table 1)  #define byte    SIOIndex    //This parameter is represented from Note1  #define byte    SIOData    //This parameter is represented from Note2  #define    void    IOWriteByte(byte IOPort, byte Value);  #define    byte    IOReadByte(byte IOPort);  // Digital Input Status relative definition (Please reference to Table 2) ...
  • Page 109 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ // Digital Output control relative definition (Please reference to Table 3)  #define byte    DOutput1LDN    // This parameter is represented from Note27  #define byte    DOutput1Reg    // This parameter is represented from Note28  #define byte    DOutput1Bit    // This parameter is represented from Note29  #define byte    DOutput1Val    // This parameter is represented from Note30  #define byte    DOutput2LDN    // This parameter is represented from Note31  #define byte ...
  • Page 110 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ Main VOID    (){    Boolean PinStatus ;      // Procedure : AaeonReadPinStatus    // Input :    //  Example, Read Digital I/O Pin 3 status  // Output :  //  InputStatus :  //    0: Digital I/O Pin level is low  //    1: Digital I/O Pin level is High ...
  • Page 111 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ AaeonReadPinStatus(byte LDN, byte Register, byte BitNum) Boolean    {    Boolean PinStatus ;      PinStatus = SIOBitRead(LDN, Register, BitNum);    Return PinStatus ;  }  AaeonSetOutputLevel(byte LDN, byte Register, byte BitNum, byte Value) VOID    {    ConfigToOutputMode(LDN, Register, BitNum);    SIOBitSet(LDN, Register, BitNum, Value);  ************************************************************************************ Appendix E Electrical Specifications for I/O Ports...
  • Page 112 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ SIOEnterMBPnPMode() VOID    {    IOWriteByte(SIOIndex, 0x87);    IOWriteByte(SIOIndex, 0x87);  }    SIOExitMBPnPMode() VOID    {    IOWriteByte(SIOIndex, 0xAA);  }    SIOSelectLDN(byte LDN) VOID    {  IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 ...
  • Page 113 M i n i - I T X E M B - Q M 8 7 A ************************************************************************************ SIOBitRead(byte LDN, byte Register, byte BitNum) Boolean    {    Byte TmpValue;      SIOEnterMBPnPMode();  SIOSelectLDN(LDN);  IOWriteByte(SIOIndex, Register);  TmpValue = IOReadByte(SIOData);    TmpValue &= (1 << BitNum);    SIOExitMBPnPMode();    If(TmpValue == 0)      Return 0;    Return 1; ...

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