NXP Semiconductors MPC556 Manuals

Manuals and User Guides for NXP Semiconductors MPC556. We have 1 NXP Semiconductors MPC556 manual available for free PDF download: User Manual

NXP Semiconductors MPC556 User Manual (967 pages)

Brand: NXP Semiconductors | Category: Motherboard | Size: 11 MB

Table of Contents
3
Block Diagram
51
MPC555 / MPC556 Features
52
MPC555 / MPC556 Address Map
55
MPC555 / MPC556 Memory Map
56
MPC555 / MPC556 Internal Memory Map
57
- Signal Descriptions
  59
Packaging and Pinout Descriptions
59
MPC555 / MPC556 Case Dimensions and Packaging
60
MPC555 / MPC556 Pinout Data
61
Pin Functionality
64
Signal Descriptions
70
- USIU Pads
  70
  - Addr[8:31]/Sgpioa[8:31]
    70
  - Data[0:31]/Sgpiod[0:31]
    71
  - Irq[0]/Sgpioc[0]
    71
  - Irq[1]/Rsv/Sgpioc[1]
    71
  - Irq[2]/Cr/Sgpioc[2]/Mts
    71
  - Irq[3]/Kr/Retry/Sgpioc[3]
    71
  - Irq[4]/At[2]/Sgpioc[4]
    72
  - Irq[5]/Sgpioc[5]/Modck[1]
    72
  - Irq[6:7]/Modck[2:3]
    72
  - Tsiz[0:1]
    72
  - Rd/Wr
    73
  - Burst
    73
  - Bdip
    73
    
    Tea
    73
    
    Rstconf/Texp
    74
    
    Bi/Sts
    74
    
    Cs[0:3]
    74
    
    We[0:3]/Be[0:3]/At[0:3]
    75
    
    Poreset
    75
    
    Hreset
    75
    
    Sreset
    75
    
    Sgpioc[6]/Frz/Ptr
    75
    
    Sgpioc[7]/Irqout/Lwp[0]
    76
    
    Bg/Vf[0]/Lwp[1]
    76
    
    Br/Vf[1]/Iwp[2]
    76
    
    Bb/Vf[2]/Iwp[3]
    76
    
    Iwp[0:1]/Vfls[0:1]
    77
    
    Tms
    77
    
    Tdi/Dsdi
    77
    
    Tck/Dsck
    77
    
    Tdo/Dsdo
    77
    
    Trst
    78
    
    Xtal
    78
    
    Extal
    78
    
    Xfc
    78
    
    Clkout
    78
    
    Extclk
    78
    
    Vddsyn
    78
    
    Vsssyn
    79
    
    Engclk/Buclk
    79
  - Qsmcm Pads
    79
    
    Pcs0/Ss/Qgpio[0]
    79
    
    Pcs(1:3)/Qgpio[1:3]
    79
    
    Miso/Qgpio[4]
    79
    
    Mosi/Qgpio[5]
    80
    
    Sck/Qgpio[6]
    80
    
    Txd[1:2]/Qgpo[1:2]
    80
    
    Rxd[1:2]/Qgpi[1:2]
    80
    
    Eck
    80
  - Mios Pads
    81
    
    Mda[11], [13]
    81
    
    Mda[12], [14]
    81
    
    Mda[15], [27:31]
    81
    
    Mpwm[0:3], [16:19]
    81
    
    Vf[0:2]/Mpio32B[0:2]
    81
Mpc555 / Mpc555
81
- Vfls[0:1]/Mpio32B[3:4]
  81
- Mpio32B[5:15]
  82
- Tpu_A/Tpu_B Pads
  82
  - Tpuch[0:15]_[A:b]
    82
  - T2Clk
    82
  - Qadc_A/Qadc_B Pads
    82
    
    Etrig[1:2]
    82
    
    An[0]/Anw/Pqb[0]_[A:b]
    82
    
    An[1]/Anx/Pqb[1]_[A:b]
    83
    
    An[2]/Any/Pqb[2]_[A:b]
    83
    
    An[3]/Anz/Pqb[3]_[A:b]
    83
    
    An[48:51]/Pqb[4:7]_[A:b]
    83
    
    An[52:54]/Ma[0:2]/Pqa[0:2]_[A:b]
    84
    
    An[55:59]/Pqa[3:7]_[A:b]
    84
    
    Vrh
    84
    
    Vrl
    84
    
    Vdda
    84
    
    Vssa
    84
  - Toucan_A/Toucan_B Pads
    84
    
    Cntx0_[A:b]
    84
    
    Cnrx0_[A:b]
    85
  - Cmf Pads
    85
    
    Epee
    85
    
    Vpp
    85
    
    Vddf
    85
    
    Vssf
    85
  - Global Power Supplies
    85
    
    Vddl
    85
    
    Vddh
    85
    
    VDDI
    86
    
    Vssi
    86
    
    Kapwr
    86
    
    Vddsram
    86
    
    Vss
    86
- Reset State
  86
Examples
89
- Special Pull Resistor Disable Control (SPRDS)
  90
- Pin Reset States
  90
- Pad Types
  95
  - Pad Interface Signals
    95
  - Three-Volt Output Pad
    96
    
    Type a Interface
    96
    
    Type B Interface (Clock Pad)
    97
  - Three-Volt Input Pad
    97
    
    Type C Interface
    98
    
    Type CH Interface
    98
    
    Type CNH Interface
    99
    
    Type D Interface
    99
  - Three-Volt Input/Output Pad
    99
    
    Type E Interface
    100
    
    Type EOH Interface
    100
    
    Type F Interface
    101
    
    Type G Interface
    102
  - Five-Volt Input/Output Pad
    103
    
    Type H Interface
    103
    
    Type I Interface
    104
    
    Type IH Interface
    105
    
    Type J Interface
    106
    
    Type JD Interface
    107
  - Type K Interface (EPEE Pad)
    108
  - Analog Pads
    109
    
    Type L Interface (QADC Port A)
    109
    
    Type M Interface (QADC Port B)
    110
    
    Type N Interface (ETRIG)
    111
  - Pads with Fast Mode
    111
    
    Type O Interface (QSMCM Pads)
    111
    
    Type P Interface (TPU and MIOS Pads)
    112
  - Input, 5V Output Pads
    113
    
    Output (Type Q)
    113
    
    Type R Interface
    114
    
    Output for Clock Pad
    115
- Pad Groups
  115
- Pin Names and Abbreviations
  116
  - Central Processing Unit
    123
- RCPU Features
  123
- RCPU Block Diagram
  124
Mpc555 / Mpc555
89
Mpc555 / Mpc555
124
- Instruction Sequencer
  125
- Independent Execution Units
  126
  - Branch Processing Unit (BPU)
    127
  - Integer Unit (IU)
    127
  - Load/Store Unit (LSU)
    128
  - Floating-Point Unit (FPU)
    128
- Levels of the Powerpc Architecture
  129
- RCPU Programming Model
  129
- RCPU Programming Model
  130
- Powerpc UISA Register Set
  133
- Powerpc VEA Register Set - Time Base
  141
- Powerpc OEA Register Set
  142
- Instruction Set
  150
  - Instruction Set Summary
    151
  - Recommended Simplified Mnemonics
    155
  - Calculating Effective Addresses
    155
- Exception Model
  156
  - Exception Classes
    156
  - Ordered Exceptions
    156
  - Unordered Exceptions
    156
  - Precise Exceptions
    157
Mpc555 / Mpc555
157
- Exception Vector Table
  157
- Instruction Timing
  158
Basic Instruction Pipeline
159
- Powerpc User Instruction Set Architecture (UISA)
  160
  - Computation Modes
    160
  - Reserved Fields
    160
  - Classes of Instructions
    160
  - Exceptions
    161
  - The Branch Processor
    161
  - Instruction Fetching
    161
  - Branch Instructions
    161
    
    Invalid Branch Instruction Forms
    161
    
    Branch Prediction
    161
  - The Fixed-Point Processor
    161
    
    Fixed-Point Instructions
    161
  - Floating-Point Processor
    162
    
    General
    162
    
    Optional Instructions
    162
  - Load/Store Processor
    162
    
    Fixed-Point Load with Update and Store with Update Instructions
    163
    
    Fixed-Point Load and Store Multiple Instructions
    163
    
    Fixed-Point Load String Instructions
    163
    
    Storage Synchronization Instructions
    163
    
    Floating-Point Load and Store with Update Instructions
    163
    
    Floating-Point Load Single Instructions
    163
    
    Floating-Point Store Single Instructions
    163
    
    Optional Instructions
    164
    
    Little-Endian Byte Ordering
    164
- Powerpc Virtual Environment Architecture (VEA)
  164
- POWERPC Operating Environment Architecture (OEA)
  165
  - Branch Processor Registers
    165
    
    Machine State Register (MSR)
    165
    
    Branch Processors Instructions
    165
  - Fixed-Point Processor
    165
    
    Special Purpose Registers
    165
  - Storage Control Instructions
    166
  - Interrupts
    166
    
    System Reset Interrupt
    166
Mpc555 / Mpc555
166
Burst Buffer Block Diagram
177
Burst Buffer Features
178
Instruction Vocabularybased Compression Model Main Principles
179
Example of Compressed Code
181
Code Compression Process (Phase A)
188
- Decompression
  189
- Compression Environment Initialization
  190
Modes of Operation
190
- Normal Operation
  191
- Slave Operation
  191
- Reset Operation
  191
- Debug Mode Operation
  191
- Standby Mode Operation
  191
- Burst Operation
  191
- Error Detection
  192
Exception Table Relocation
192
- Exception Table Relocation Operation
  193
Exception Table Entries Mapping
195
Burst Buffer Programming Model
196
Module Overview
203
SIU Architecture
204
USIU Powerpc Memory Map
207
- USIU Pins Multiplexing
  211
- Arbitration Support
  212
External Master Modes
213
- Address Decoding for External Accesses
  214
Interrupt Controller
216
- SIU Interrupt Sources Priority
  219
Hardware Bus Monitor
220
MPC555 / MPC556 Time Base (TB)
221
Real-Time Clock (RTC)
222
Periodic Interrupt Timer (PIT)
223
Software Watchdog Timer (SWT)
224
- Freeze Operation
  226
- System Configuration Registers
  227
  - Internal Memory Map Register
    230
  - External Master Control Register (EMCR)
    231
- SIU Interrupt Registers
  233
  - SIU Interrupt Edge Level Register (SIEL)
    234
- System Protection Registers
  235
  - Software Service Register (SWSR)
    236
  - Transfer Error Status Register (TESR)
    237
- System Timer Registers
  238
- General-Purpose I/O Registers
  244
  - SGPIO Control Register (SGPIOCR)
    245
  - Reset Operation
    247
- Hard Reset
  248
- Loss of Lock
  249
Data Coherency During Reset
250
Reset Status Register
251
Reset Configuration
252
Reset Configuration Sampling Timing Requirements
257
- Hard Reset Configuration Word
  258
- Soft Reset Configuration
  259
- Overview
  261
Clock Unit Block Diagram
262
System Clock Sources
263
- Frequency Multiplication
  264
- PLL Pins
  265
System Clock During PLL Loss of Lock
266
MPC555 / MPC556 Internal Clock Signals
267
General System Clocks
269
General System Clocks Select
270
Timing Diagram
271
- Clkout
  272
Clock Source Switching
273
Clock Source Flow Chart
274
Low-Power Modes
275
- Power Mode Descriptions
  276
  - Exiting from Normal-Low Mode
    277
  - Exiting from Power-Down Mode
    278
MPC555 / MPC556 Low-Power Modes Flow Diagram
279
Basic Power Structure
280
- Vddsyn, Vsssyn
  281
- Keep Alive Power
  282
  - Keep Alive Power Registers Lock Mechanism
    283
VDDSRAM Supply Failure Detection
285
No Standby, no KAPWR, All System Power On/Off
286
Clocks Unit Programming Model
288
Bus Control Signals
298
Bus Interface Signal Descriptions
299
Bus Operations
303
Basic Transfer Protocol
304
Basic Flow Diagram of a Single Beat Read Cycle
305
Single Beat Read Cycle–Basic Timing–Zero Wait States
306
- Single Beat Write Flow
  307
Basic Flow Diagram of a Single Beat Write Cycle
308
Single Beat Basic Write Cycle Timing, Zero Wait States
309
- Single Beat Flow with Small Port Size
  310
- Burst Transfer
  311
- Burst Mechanism
  312
Basic Flow Diagram of a Burst Read Cycle
314
Burst-Read Cycle–32-Bit Port Size–Zero Wait State
315
Burst-Read Cycle–32-Bit Port Size–One Wait State
316
Burst-Read Cycle–32-Bit Port Size–Wait States between Beats
317
Burst-Read Cycle, 16-Bit Port Size
318
Basic Flow Diagram of a Burst Write Cycle
319
Burst-Write Cycle, 32-Bit Port Size, Zero Wait States
320
Burst-Inhibit Cycle, 32-Bit Port Size (Emulated Burst)
321
Non-Wrap Burst with Three Beats
322
Non-Wrap Burst with One Data Beat
323
- Alignment and Packaging of Transfers
  324
Interface to Different Port Size Devices
325
- Arbitration Phase
  326
  - Bus Request
    327
  - Bus Grant
    328
  - Internal Bus Arbiter
    329
- Address Transfer Phase Signals
  331
  - Transfer Start
    332
  - Transfer Size
    333
  - Burst Data in Progress
    334
  - Burst Inhibit
    335
- Storage Reservation
  336
Reservation on Local Bus
337
Reservation on Multilevel Bus Hierarchy
338
- Bus Exception Control Cycles
  339
Retry Transfer Timing–Internal Arbiter
340
Retry Transfer Timing–External Arbiter
341
Retry on Burst Cycle
342
- Termination Signals Protocol Summary
  343
Basic Flow of an External Master Read Access
344
Basic Flow of an External Master Write Access
345
- Peripheral Mode: External Master Reads from MPC555 / MPC556 — Two Wait States
  346
- Contention Resolution on External Bus
  348
Flow of Retry of External Master Read Access
349
- Show Cycle Transactions
  350
Instruction Show Cycle Transaction
351
Data Show Cycle Transaction
352
Overview
353
Memory Controller Block Diagram
354
Memory Controller Architecture
355
- Associated Registers
  356
- Write-Protect Configuration
  357
Chip-Select Timing
358
- Memory Devices Interface Example
  359
- Peripheral Devices Interface Example
  360
Peripheral Devices Interface
361
- Relaxed Timing Examples
  362
- Extended Hold Time on Read Accesses
  366
Consecutive Accesses (Write after Read, EHTR = 0)
367
Consecutive Accesses (Write after Read, EHTR = 1)
368
- Summary of GPCM Timing Options
  370
Global (Boot) Chip-Select Operation
372
Write and Byte Enable Signals
373
Aliasing Phenomena Illustration
375
Memory Controller External Master Support
376
Synchronous External Master Configuration for Gpcm–Handled Memory Devices
377
Synchronous External Master Basic Access (GPCM Controlled)
378
General Features
387
L2U Block Diagram
388
- Normal Mode
  389
Data Memory Protection
390
- Associated Registers
  391
Region Base Address Example
392
- L-Bus Memory Access Violations
  393
- Reserved Location (Bus) and Possible Actions
  394
L-Bus Show Cycle Support
395
- Show Cycle Protocol
  396
- L-Bus Read Show Cycle Flow
  397
L2U Programming Model
398
- U-Bus Access
  399
- Region Base Address Registers (L2U_Rbax)
  400
- Region Attribute Registers (L2U_Rax)
  401
- Features
  403
UIMB Block Diagram
404
Interrupt Operation
405
Interrupt Sources and Levels on IMB
406
Time-Multiplexing Protocol for IRQ Pins
407
Interrupt Synchronizer
408
- Programming Model
  409
- Test Control Register (UTSTCREG)
  410
  - Overview
    413
  - Features
    414
- Port a Pin Functions
  415
- Port B Pin Functions
  416
- Multiplexed Analog Input Pins
  417
QADC64 Bus Interface
418
- Supervisor/Unrestricted Address Space
  419
- Port Data Register
  420
External Multiplexing Operation
421
Analog Input Channels
422
Analog Subsystem
423
- Conversion Cycle Times
  424
  - Amplifier Bypass Mode Conversion Timing
    425
- Front-End Analog Multiplexer
  426
- Queue Priority
  427
QADC64 Queue Operation with Pause
428
- Queue Boundary Conditions
  429
- Scan Modes
  430
  - Continuous-Scan Modes
    433
- QADC64 Clock (QCLK) Generation
  436
QADC64 Clock Subsystem Functions
438
QADC64 Clock Programmability Examples
440
- Periodic/Interval Timer
  441
- Interrupt Sources
  442
- Interrupt Register
  443
- QADC64 Module Configuration Register
  445
- Port A/B Data Register
  446
- Port Data Direction Register
  447
- QADC64 Control Register 1 (QACR1)
  448
- QADC64 Control Register 2 (QACR2)
  450
- QADC64 Status Register 0 (QASR0)
  452
- QADC64 Status Register 1 (QASR1)
  454
- Conversion Command Word Table
  455
QADC64 Conversion Queue Operation
456
- Result Word Table
  461
- Overview
  463
Signal Descriptions
464
QSMCM Global Registers
466
- Low-Power Stop Operation
  467
- QSMCM Interrupts
  468
- QSMCM Configuration Register (QSMCMMCR)
  469
- QSMCM Test Register (QTEST)
  470
QSMCM Pin Control Registers
471
Queued Serial Peripheral Interface
475
QSPI Block Diagram
476
- QSPI Registers
  477
  - QSPI Control Register 0
    478
  - QSPI Control Register 1
    480
  - QSPI Control Register 3
    481
  - QSPI Status Register
    482
Qspi Ram
483
- Receive RAM
  484
- QSPI Pins
  485
- QSPI Operation
  486
  - Enabling, Disabling, and Halting the SPI
    487
  - QSPI Interrupts
    488
Flowchart of QSPI Initialization Operation
489
Flowchart of QSPI Master Operation (Part 1)
490
Flowchart of QSPI Master Operation (Part 2)
491
Flowchart of QSPI Master Operation (Part 3)
492
Flowchart of QSPI Slave Operation (Part 1)
493
Flowchart of QSPI Slave Operation (Part 2)
494
- Master Mode Operation
  495
  - Clock Phase and Polarity
    496
  - Delay before Transfer
    497
  - Transfer Length
    498
  - Master Wraparound Mode
    499
  - Description of Slave Operation
    501
- Slave Wraparound Mode
  502
- Mode Fault
  503
SCI Transmitter Block Diagram
504
SCI Receiver Block Diagram
505
- SCI Registers
  506
- SCI Control Register 0
  507
- SCI Status Register (Scxsr)
  509
- SCI Data Register (Scxdr)
  511
- SCI Pins
  512
  - Serial Formats
    513
  - Parity Checking
    514
  - Receiver Operation
    516
  - Receiver Functional Operation
    518
  - Idle-Line Detection
    519
  - Receiver Wake-Up
    520
- Queued SCI1 Status and Control Registers
  521
  - QSCI1 Status Register
    523
- QSCI1 Additional Transmit Operation Features
  524
- QSCI1 Transmit Flow Chart Implementing the Queue
  526
Queue Transmit Software Flow
527
MIOS1 Features
537
Submodule Numbering, Naming and Addressing
539
Block Diagram
540
MIOS1 Block Diagram
541
MIOS1 Bus System
542
MIOS1 Memory Map
543
MIOS1 I/O Ports
544
- MIOS1 Vector Register
  545
- MBISM Interrupt Registers
  546
  - MIOS1 Interrupt Level Register 1 (MIOS1LVL1)
    547
MIOS Counter Prescaler Submodule (MCPSM)
548
- MCPSM Status/Control Register (MCPSMCSCR)
  549
- MIOS Modulus Counter Submodule (MMCSM) Registers
  551
  - MMCSM Up-Counter Register (MMCSMCNT)
    552
  - MMCSM Status/Control Register (MMCSMSCR)
    553
MIOS Double Action Submodule (MDASM)
554
- MIOS Double Action Submodule (MDASM) Registers
  555
MIOS Pulse Width Modulation Submodule (MPWMSM)
561
- MIOS Pulse Width Modulation Submodule (MPWMSM) Registers
  562
  - MPWMSM Period Register (MPWMSMPERR)
    563
  - MPWMSM Counter Register (MPWMSMCNTR)
    564
MIOS 16-Bit Parallel Port I/O Submodule (MPIOSM)
566
MIOS1 Function Examples
574
MIOS1 Example: Double Capture Pulse Width Measurement
575
Features
583
External Pins
584
Toucan Architecture
585
- Common Fields for Extended and Standard Format Frames
  586
- Fields for Extended Format Frames
  588
- Message Buffer Activation/Deactivation Mechanism
  589
- Bit Timing
  590
  - Configuring the Toucan Bit Timing
    591
- Time Stamp
  592
Toucan Operation
593
- Transmit Process
  594
- Overload Frames
  598
Low-Power Stop Mode
599
- Auto Power Save Mode
  600
  - Interrupts
    601
Programmer's Model
602
- Toucan Module Configuration Register
  603
Toucan Message Buffer Memory Map
605
- Control Register 0
  607
- Toucan Test Configuration Register
  608
- Control Register 1
  609
- Control Register 2
  610
- Prescaler Divide Register
  611
- Receive Global Mask Registers
  613
- Receive Buffer 14 Mask Registers
  614
- Error Counters
  615
- Interrupt Mask Register
  616
- Interrupt Flag Register
  617
Overview
619
TPU3 Components
620
- Host Interface
  621
- Interchannel Communication
  622
- TPU3 Interrupts
  623
- Prescaler Control for TCR2
  625
Programming Model
626
- TPU Module Configuration Register
  628
- TPU3 Test Configuration Register
  630
- Development Support Status Register
  632
- Channel Interrupt Enable Register
  633
- Host Sequence Registers
  634
- Host Service Request Registers
  635
- Channel Priority Registers
  636
- Channel Interrupt Status Register
  637
- TPU3 Module Configuration Register 2
  638
- TPU Module Configuration Register 3
  639
- TPU3 Test Registers
  640
Time Functions
641
Features
643
DPTRAM Configuration and Block Diagram
644
- DPTRAM Module Configuration Register (DPTMCR)
  645
- DPTRAM Test Register
  646
- Ram Base Address Register (RAMBAR)
  647
- MISC Counter (MISCNT)
  648
Reset Operation
649
- Freeze Operation
  650
Introduction
653
- MPC555 / MPC556 CMF Features
  654
Programming Model
656
Array Read Operation
669
Programming the CMF Array
670
Program State Diagram
672
- Program Margin Reads
  674
- Over-Programming
  675
Erase State Diagram
677
- Erase Margin Reads
  678
Voltage Control for Programming and Erasing
679
Pin Descriptions
688
- FLASH Program/Erase Voltage Conditioning
  689
VPP and VDDL Power Switching
690
- Reset Operation
  691
- Emulation Operation
  692
  - Features
    693
  - Programming Model
    694
- SRAM Test Register (SRAMTST)
  695
- Overview
  697
- Program Trace Cycle
  698
  - Instruction Queue Status Pins — VF [0:2]
    699
  - History Buffer Flushes Status Pins— VFLS [0..1]
    700
- Sequential Instructions Marked as Indirect Branch
  701
  - Detecting the Trace Window Start Address
    702
  - Detecting the Assertion/Negation of VSYNC
    703
- Instruction Fetch Show Cycle Control
  704
Watchpoints and Breakpoint Support in the CPU
706
- Internal Watchpoints and Breakpoints
  707
Restrictions
709
- Examples
  710
- Context Dependent Filter
  711
- Generating Six Compare Types
  712
- Load/Store Support
  713
Load/Store Support General Structure
716
- Watchpoint Counters
  717
Functional Diagram of MPC555 / MPC556 Debug Mode Support
719
- Debug Mode Support
  720
Debug Mode Logic
721
- Debug Mode Enable Vs. Debug Mode Disable
  722
Debug Mode Reset Configuration
723
Asynchronous Clock Serial Communications
731
Synchronous Self Clock Serial Communication
732
Enabling Clock Mode Following Reset
733
Download Procedure Code Example
738
Software Monitor Debugger Support
739
JTAG Interface Block Diagram
755
JTAG Signal Descriptions
756
Operating Frequency
757
Instruction Register
758
- Extest
  759
- Clamp
  760
Non-IEEE 1149.1-1990 Operation
761
Output Pin Cell (O.pin)
762
Output Control Cell (IO.CTL)
763
- Appendix A
  815
- Appendix B
  815
- Appendix C
  815
- Appendix D
  815
D.1 Overview
815
D.2 Programmable Time Accumulator (PTA)
818
D-2 PTA Parameters
819
D.3 Queued Output Match TPU Function (QOM)
820
D-3 QOM Parameters
821
D.4 Table Stepper Motor (TSM)
822
- D-4 TSM Parameters — Master Mode
  823
- D-5 TSM Parameters — Slave Mode
  824
D.5 Frequency Measurement (FQM)
825
D-6 FQM Parameters
826
D.6 Universal Asynchronous Receiver/Transmitter (UART)
827
- D-7 UART Transmitter Parameters
  828
- D-8 UART Receiver Parameters
  829
D.7 New Input Capture/Transition Counter (NITC)
830
D-9 NITC Parameters
831
D.8 Multiphase Motor Commutation (COMM)
832
D-10 COMM Parameters (Part 1 of 2)
833
D.9 Hall Effect Decode (HALLD)
834
D-12 HALLD Parameters
835
D.10 Multichannel Pulse-Width Modulation (MCPWM)
836
- D-13 MCPWM Parameters — Master Mode
  837
- D-14 MCPWM Parameters — Slave Edge-Aligned Mode
  838
D.11 Fast Quadrature Decode TPU Function (FQD)
843
- D-19 FQD Parameters — Primary Channel
  844
- D-20 FQD Parameters — Secondary Channel
  845
D.12 Period/Pulse-Width Accumulator (PPWA)
846
D-21 PPWA Parameters
847
D.13 Output Compare (OC)
848
D-22 OC Parameters
849
D.14 Pulse-Width Modulation (PWM)
850
D-23 PWM Parameters
851
D.15 Discrete Input/Output (DIO)
852
D-24 DIO Parameters
853
D.16 Synchronized Pulse-Width Modulation (SPWM)
854
- D-25 SPWM Parameters, Part 1 of 2
  855
- D-26 SPWM Parameters, Part 2 of 2
  856
D.17 Read / Write Timers and Pin TPU Function (RWTPIN)
857
D-27 RWTPIN Parameters
858
D.18 ID TPU Function (ID)
859
D-28 ID Parameters
860
D.19 Serial Input/Output Port (SIOP)
861
- D.19.1 Parameters
  862
  - D-30 SIOP Parameters
    863
  - D.19.1.1 Chan_Control
    864
- D.19.2 Host CPU Initialization of the SIOP Function
  865
  - D.19.3.1 XFER_SIZE Greater than 16
    866
  - D-31 SIOP Function Data Transition Example
    867
E.1 Introduction
869
E.2 MPC555 / MPC556 Family Power Distribution
870
E-2 MPC555 / MPC556 Family Power Distribution Diagram — 5 V and Analog
871
E.3 PLL and Crystal Oscillator External Components
872
- Appendix E
  873
- E.3.2 KAPWR Filtering
  873
- E.3.3 PLL External Components
  874
E.4 Clock Oscillator and PLL External Components Layout Requirements
875
- E.4.2 Grounding/Guarding
  876
- Appendix F
  877
F.1 Introduction
877
- Appendix G G.2 Target Failure Rate
  880
- G.4.3 Testing Characteristics
  881
- G.5.1 Thermal References:
  883
G.6 ESD Protection
884
G.7 DC Electrical Characteristics
885
G.8 Oscillator and PLL Electrical Characteristics
890
G.10 FLASH Electrical Characteristics
891
- G.10.1 Flash Module Life
  892
- G.10.2 Programming and Erase Algorithm
  893
G.11 Generic Timing
894
G.12 Interrupt Timing
917
G.13 Debug Port Timing
918
- G-20 Debug Port Clock Input Timing
  919
- G-21 Debug Port Timings
  920
G.14 Reset Timing
921
G.15 IEEE 1149.1 Electrical Characteristics
925
G.16 QADC64 Electrical Characteristics
930
G.17 QSMCM Electrical Characteristics
931
- G-29 QSPI Timing — Master, CPHA = 0
  933
- G-31 QSPI Timing — Slave, CPHA = 0
  934
G.18 GPIO Electrical Characteristics
935
G.20 Toucan Electrical Characteristics
936
G.21 MIOS Timing Characteristics
937
H.1 Electrical Characteristics
947
- Appendix H
  949
- H.1.1 Flash Module Life
  949

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