Page 1 Rev. 1 — 16 December 2011 User manual Document information Info Content Keywords ARM, ARM7, embedded, 32-bit, MPPT, MPT612 Abstract This document describes all aspects of the MPT612, an IC designed for applications using solar photovoltaic (PV) cells, or fuel cells.
Page 2 UM10413 NXP Semiconductors MPT612 User manual Revision history Date Description 20111216 initial version Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com UM10413 All information provided in this document is subject to legal disclaimers.
Page 3: Introduction
15 kB of flash memory available for application software. In this user manual, solar PV terminology is primarily used as an example. However, the MPT612 is equally useful for fuel cells or any other DC source which has MPP characteristics.
Page 4: Applications
ARM Peripheral Bus (APB, a compatible superset of ARM AMBA Advanced Peripheral Bus) for connecting on-chip peripheral functions The MPT612 configures the ARM7TDMI-S processor core in little endian byte order. UM10413 All information provided in this document is subject to legal disclaimers.
Page 5: Arm7Tdmi-S Processor
30 % over Thumb mode. 5.2 On-chip flash memory system The MPT612 incorporates a 32 kB flash memory system. This memory can be used for both code and data storage. Various methods can be used to program flash memory, such as using: •...
Page 6: On-Chip Static Ram (Sram)
The entire flash memory is available for user code as the bootloader resides in a separate memory. The MPT612 flash memory provides a minimum of 100 000 erase/write cycles and 20 years of data-retention memory. 5.3 On-chip Static RAM (SRAM) On-chip static RAM can be used for code and/or data storage.
Page 7: Memory Addressing
UM10413 NXP Semiconductors MPT612 User manual 7. Memory addressing 7.1 Memory maps The MPT612 incorporates several distinct memory regions, shown in Figure 2 Figure Figure 2 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping, which is described later in this section.
Page 8 UM10413 NXP Semiconductors MPT612 User manual 0xFFFF FFFF 4.0 GB AHB PERIPHERALS 0xFFE0 0000 4.0 GB - 2 MB 0xFFDF FFFF RESERVED 0xF000 0000 3.75 GB 0xEFFF FFFF RESERVED 0xE020 0000 3.5 GB + 2 MB 0xE01F FFFF APB PERIPHERALS 3.5 GB...
Page 9 UM10413 NXP Semiconductors MPT612 User manual (8-bit) or half-word (16-bit) accesses at smaller boundaries. This method requires all word and half-word registers to be accessed at once. For example, it is not possible to read or write the upper byte of a word register separately.
Page 10: Mpt612 Memory Remapping And Boot Block
7.2 MPT612 memory remapping and boot block 7.2.1 Memory map concepts and operating modes Basically, each memory area in the MPT612 has a "natural" location in the memory map, and is the address range for which code residing in that area is written. Most memory spaces remain permanently fixed in the same location, eliminating the need to design parts of the code to run in different address ranges.
Page 11: Memory Remapping
Remark: Identified as reserved in ARM documentation, used by the bootloader as the valid user program key. Details described in Section 25.5.2 on page 218. 0x0000 0018 0x0000 001C Table 4. MPT612 memory mapping modes Mode Activation Usage Boot hardware bootloader always executes after any reset. Boot block interrupt...
Page 12: Prefetch Abort And Data Abort Exceptions
32 kB flash) 7.3 Prefetch abort and data abort exceptions If an access is attempted for an address that is in a reserved or unassigned address region, the MPT612 generates the appropriate bus cycle abort exception. The regions are: •...
Page 13: Memory Acceleration Module (Mam)
Essentially, the Memory Accelerator Module (MAM) attempts to have the next ARM instruction that is needed in its latches in time to prevent CPU fetch stalls. The MPT612 uses one bank of flash memory, compared to the two banks used on predecessor devices.
Page 14: Mam Blocks
8.2.1 Flash memory bank There is one bank of flash memory on the MPT612 MAM. Flash programming operations are handled as a separate function and not controlled by the MAM. A separate boot block in ROM contains flash programming algorithms that can be called by the application program, and a loader that can be run to allow serial programming of flash memory.
Page 15: Instruction Latches And Data Latches
You must ensure that an unwanted watchdog reset does not cause a system failure while programming or erasing the flash memory. To preclude the possibility of stale data being read from the flash memory, the MPT612 MAM holding latches are automatically invalidated at the beginning of any flash programming or erase operation.
Page 16: Mam Configuration
UM10413 NXP Semiconductors MPT612 User manual Mode 1: MAM partially enabled. If the data is present, sequential instruction accesses are fulfilled by the holding latches. Instruction prefetch is enabled. Non-sequential instruction accesses initiate flash read operations (see Table 5, note 2). This means that all branches cause memory fetches.
Page 17: Mam Control Register (Mamcr - 0Xe01F C000)
UM10413 NXP Semiconductors MPT612 User manual Table 7. Summary of MAM registers Name Description Access Reset Address value MAMCR MAM control register. Determines MAM functional 0xE01F C000 mode: to what extent the MAM performance enhancements are enabled; see Table MAMTIM MAM timing control. Determines number of clocks...
Page 18: Mam Usage Notes
UM10413 NXP Semiconductors MPT612 User manual Table 9. MAM Timing register (MAMTIM - address 0xE01F C004) bit description Symbol Value Description Reset value MAM_fetch_ 0 - reserved cycle_timing 1 - MAM fetch cycles are 1 processor clock (CCLK) in duration...
Page 19: Description
UM10413 NXP Semiconductors MPT612 User manual 9.2 Description The Vectored Interrupt Controller (VIC) takes 32 interrupt request inputs and assigns them to 3 categories, FIQ, vectored IRQ, and non-vectored IRQ. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted.
Page 20 UM10413 NXP Semiconductors MPT612 User manual Table 11. VIC register map …continued Name Description Access Reset Address value VICSoftIntClear software interrupt clear register. Allows software to clear one or more 0xFFFF F01C bits in the software interrupt register. VICProtection protection enable register. Allows limiting access to the VIC registers 0xFFFF F020 by software running in privileged mode.
Page 21: Vic Registers
UM10413 NXP Semiconductors MPT612 User manual Table 11. VIC register map …continued Name Description Access Reset Address value VICVectCntl13 vector control 13 register 0xFFFF F234 VICVectCntl14 vector control 14 register 0xFFFF F238 VICVectCntl15 vector control 15 register 0xFFFF F23C Reset value reflects the data stored in used bits only. It does not include content of reserved bits.
Page 22: Raw Interrupt Status Register (Vicrawintr -
UM10413 NXP Semiconductors MPT612 User manual Table 14. Software interrupt clear register (VICSoftIntClear - address 0xFFFF F01C) bit allocation Reset value: 0x0000 0000 Symbol TIMER3 reserved Access Symbol I2C1 EINT2 Access Symbol EINT1 EINT0 SSP/SPI1 SPI0 I2C0 Access Symbol UART1...
Page 23: Interrupt Enable Register (Vicintenable -
UM10413 NXP Semiconductors MPT612 User manual Table 17. Raw interrupt status register (VICRawIntr - address 0xFFFF F008) bit description Symbol Value Description Reset value 31:0 Table 16 does not assert hardware or software interrupt request with this bit number asserts hardware or software interrupt request with this bit number 9.4.4 Interrupt enable register (VICIntEnable - 0xFFFF F010)
Page 24: Interrupt Select Register (Vicintselect - 0Xffff F00C)
UM10413 NXP Semiconductors MPT612 User manual Table 20. Software interrupt clear register (VICIntEnClear - address 0xFFFF F014) bit allocation Reset value: 0x0000 0000 Symbol TIMER3 reserved Access Symbol I2C1 EINT2 Access Symbol EINT1 EINT0 SSP/SPI1 SPI0 I2C0 Access Symbol UART1...
Page 25: Irq Status Register (Vicirqstatus - 0Xffff F000)
UM10413 NXP Semiconductors MPT612 User manual Table 23. Interrupt select register (VICIntSelect - address 0xFFFF F00C) bit description Symbol Value Description Reset value 31:0 Table 22 assigns interrupt request with this bit number to IRQ category assigns interrupt request with this bit number to FIQ category 9.4.7 IRQ Status register (VICIRQStatus - 0xFFFF F000)
Page 26: Vector Control Registers 0 To 15 (Vicvectcntl0-15 0Xffff F200 To 23C)
UM10413 NXP Semiconductors MPT612 User manual Table 26. FIQ Status register (VICFIQStatus - address 0xFFFF F004) bit allocation Reset value: 0x0000 0000 Symbol TIMER3 reserved Access Symbol I2C1 EINT2 Access Symbol EINT1 EINT0 SSP/SPI1 SPI0 I2C0 Access Symbol UART1 UART0...
Page 27: Default Vector Address Register (Vicdefvectaddr - 0Xffff F034)
UM10413 NXP Semiconductors MPT612 User manual Table 29. Vector address registers 0 to 15 (VICVectAddr0 to 15 - addresses 0xFFFF F100 to 13C) bit description Symbol Description Reset value 31:0 IRQ_vector if an interrupt request or software interrupt is enabled, classified as IRQ,...
Page 28 UM10413 NXP Semiconductors MPT612 User manual Table 33. Connection of interrupt sources to the Vectored Interrupt Controller (VIC) Block Flag(s) VIC Channel # and Hex mask Watchdog Interrupt (WDINT) 0x0000 0001 reserved for software interrupts only 0x0000 0002 ARM Core...
Page 29: Spurious Interrupts
Block diagram of the Vectored Interrupt Controller (VIC) 9.6 Spurious interrupts Spurious interrupts are possible in the ARM7TDMI based ICs such as the MPT612 due to asynchronous interrupt handling. The asynchronous character of the interrupt processing has its roots in the interaction of the core and the VIC. If the VIC state is changed between the moments when the core detects an interrupt, and the core actually processes an interrupt, problems can be generated.
Page 30: Details And Case Studies On Spurious Interrupts
UM10413 NXP Semiconductors MPT612 User manual • Application code must be set up in a way to prevent the spurious interrupts from occurring. Simple guarding of changes to the VIC cannot be enough since, for example, glitches on level-sensitive interrupts can also cause spurious interrupts.
Page 31: Workaround
UM10413 NXP Semiconductors MPT612 User manual entered due to an IRQ being received when executing the MSR instruction which disables IRQs, then bit I is set in SPSR. The routine therefore assumes that it could not have been entered via an IRQ.
Page 32: Vic Usage Notes
UM10413 NXP Semiconductors MPT612 User manual MSR cpsr_c, #I_Bit:OR:irq_MODE ;IRQ must be disabled ;FIQ enabled ;ARM state, IRQ mode This arrangement requires modification of only the IRQ handler, and FIQs can be re-enabled more quickly than by using workaround 1. However, use it only if the system can guarantee that FIQs are never disabled while IRQs are enabled.
Page 33: System Control Block
; as the one with priority 1 After any IRQ requests (SPI0, I C, UART0 or UART1) are made, the MPT612 redirects code execution to the address specified at location 0x0000 0018. For vectored and non-vectored IRQs the following instruction can be placed at 0x0000 0018: LDR pc, [pc,#-0xFF0] This instruction loads PC with the address that is present in register VICVectAddr.
Page 34: Register Description
UM10413 NXP Semiconductors MPT612 User manual Table 34. Pin summary Pin name Pin description direction XTAL1 input crystal oscillator input: input to the oscillator and internal clock generator circuits XTAL2 output crystal oscillator output: output from the oscillator amplifier EINT0...
Page 35: Crystal Oscillator
Section 10.8 “Phase-Locked Loop (PLL)” on page 43 for details and frequency limitations. The onboard oscillator in the MPT612 can operate in one of two modes: slave mode and oscillation mode. In slave mode, couple the input clock signal with a capacitor of 100 pF (C Figure drawing a), with an amplitude of at least 200 mV (RMS).
Page 36 UM10413 NXP Semiconductors MPT612 User manual MPT612 MPT612 XTAL1 XTAL2 XTAL1 XTAL2 Xtal < = > C X1 C X2 Clock aaa-000574 Fig 8. Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation, c) external...
Page 37: Xtal1 Input
UM10413 NXP Semiconductors MPT612 User manual selection true on-chip PLL used in application? false true ISP used for initial code download? false external crystal true oscillator used? false MIN f = 10 MHz MIN f = 1 MHz MIN f...
Page 38: External Interrupt Inputs
MPT612 User manual 10.5 External interrupt inputs The MPT612 includes up to three external interrupt inputs as selectable pin functions. When the pins are combined, external events can be processed as three independent interrupt signals. The external interrupt inputs can optionally be used to wake up the processor from Power-down or Deep power-down mode.
Page 39: Interrupt Wake-Up Register (Intwake - 0Xe01F C144)
(eliminating the need to disable the interrupt if the wake-up feature is not desirable in the application). If an external interrupt pin is required to be a source for waking the MPT612 from Power-down mode, the corresponding bit in register External Interrupt Flag must be cleared;...
Page 40: External Interrupt Mode Register (Extmode - 0Xe01F C148)
UM10413 NXP Semiconductors MPT612 User manual Table 39. Interrupt wake-up register (INTWAKE - address 0xE01F C144) bit description Symbol Description Reset value EXTWAKE0 if logic 1, assertion of EINT0 wakes up processor from Power-down mode EXTWAKE1 if logic 1, assertion of EINT1 wakes up the processor from...
Page 41 UM10413 NXP Semiconductors MPT612 User manual “Register description” on page 62) and enabled in register VICIntEnable (see Section 9.4 “VIC registers” on page 21) can cause interrupts from the External Interrupt function (though pins selected for other functions can cause interrupts from those functions).
Page 42: Other System Controls
Fig 11. External interrupt logic 10.6 Other system controls Some aspects of controlling MPT612 operation that do not fit into peripheral or other registers are grouped as shown below. 10.6.1 System control and status flags register (SCS - 0xE01F C1A0) Table 42.
Page 43: Memory Mapping Control Register (Memmap - 0Xe01F C040)
Oscillator (CCO). The multiplier can be an integer from 1 to 32; in practice, the multiplier value cannot be higher than 6 on the MPT612 due to the upper frequency limit of the CPU. The CCO operates in the range 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency.
Page 44: Register Description
NXP Semiconductors MPT612 User manual accidental changes to the PLL setup can result in unexpected behavior of the MPT612. A feed sequence similar to that of the watchdog timer provides the protection. Details are provided in the description of register PLLFEED.
Page 45: Pll Control Register (Pllcon - 0Xe01F C080)
PLLSTAT, Table PLLC PLL connect. If PLLC and PLLE are both set to logic 1, and after a valid PLL feed, connects PLL as clock source for MPT612. Otherwise, oscillator clock is used directly by MPT612; see register PLLSTAT, Table reserved, user software must not write logic 1s to reserved bits;...
Page 46: Pll Configuration Register (Pllcfg - 0Xe01F C084)
UM10413 NXP Semiconductors MPT612 User manual The PLL must be set up, enabled, and lock established before it can be used as a clock source. When switching from the oscillator clock to the PLL output or vice versa, internal circuitry synchronizes the operation in order to ensure that glitches are not generated. If lock is lost during operation, hardware does not ensure that the PLL is locked before it is connected nor automatically disconnects the PLL.
Page 47: Pll Interrupt
PLLC read-back for bit PLL Connect. When PLLC and PLLE are both logic 1, the PLL is connected as the clock source for the MPT612. When either PLLC or PLLE is logic 0, the PLL is bypassed and the oscillator clock is used directly by the MPT612. This bit is automatically cleared when Power-down mode is activated.
Page 48: Pll And Power-Down Mode
• CCLK is in the range 10 MHz to f (the maximum allowed frequency for the MPT612 - embedded in and determined by the system MPT612). • is in the range 156 MHz to 320 MHz. 10.8.10 Procedure for determining PLL settings If a particular application uses the PLL, its configuration can be determined as follows: 1.
Page 49: Pll Configuration Examples
P = 2. Therefore, PLLCFG[6:5] = 1 is used. 10.9 Power control The MPT612 supports three reduced power modes: Idle mode, Power-down mode, and Deep power-down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs.
Page 50: Register Description
PCON power control register. Contains control bits 0x00 0xE01F C0C0 that enable the two reduced power operating modes of the MPT612; see Table PCONP power control for peripherals register. 0x0018 17BE 0xE01F C0C4 Contains control bits that enable and disable...
Page 51: Power Control For Peripherals Register (Pconp - 0Xe01F Coc4)
UM10413 NXP Semiconductors MPT612 User manual Table 54. Power control register (PCON - address 0xE01F COCO) bit description Symbol Description Reset value Idle mode. If logic 1, causes processor clock to stop, while on-chip peripherals remain active. Any enabled interrupt from a peripheral or an external interrupt source causes processor to resume execution.
Page 52: Power Control Usage Notes
0. 10.10 Reset Reset has two sources on the MPT612: pin RESET and watchdog reset. Pin RESET is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip reset by any source starts the wake-up timer (see Section 10.12 “Wake-up...
Page 53 (1) Reset time: The reset time must be held LOW. This time depends on system parameters such as V rise time, and DD(IO) the oscillator start-up time. There are no restrictions from the MPT612 except that V , and the oscillator must be DD(IO) within the specific operating range.
Page 54: Reset Source Identification Register (Rsir - 0Xe01F C180)
UM10413 NXP Semiconductors MPT612 User manual reset to the external on-chip reset circuitry watchdog reset to reset PCON.PD WAKE-UP power TIMER down START EINT0 wake-up EINT1 wake-up COUNT2n EINT2 wake-up oscillator output (f osc ) write “1” from APB Reset...
Page 55: Register Description
UM10413 NXP Semiconductors MPT612 User manual The APB Divider serves two purposes: • provides peripherals with desired PCLK via APB bus so that they can operate at the speed chosen for the ARM processor. To achieve this, the APB bus can be slowed down to one half or one fourth of the processor clock rate.
Page 56: Wake-Up Timer
Any of the various resets can bring the MPT612 out of Power-down mode, as can the external interrupts EINT2:0 and the RTC interrupt if the RTC is operating from its own oscillator on the RTCX1-2 pins.
Page 57: Code Security Vs. Debugging
Applications in development typically need the debugging and tracing facilities in the MPT612. Later in the life cycle of an application, it can be more important to protect the application code from observation by hostile or competitive eyes. The Code Read Protection feature on the MPT612 allows an application to control whether it can be debugged or protected from observation.
Page 58: Mpt612 Pin Description
UM10413 NXP Semiconductors MPT612 User manual 11.2 MPT612 pin description The MPT612 pin functions are briefly described in Table Table 59. Pin description Symbol Type Description PIO0 to PIO31 Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. A total of 31 pins of Port 0 can be used as general purpose bidirectional digital I/Os while PIO31 is an output-only pin.
Page 59 UM10413 NXP Semiconductors MPT612 User manual Table 59. Pin description …continued Symbol Type Description PIO12/DSR1/ PIO12: general purpose input/output digital pin MAT1_0/AD5 DSR1: data set ready input for UART1 MAT1_0: PWM output for Timer 1, channel 0 AD5: ADC 0, input 5...
Page 60 UM10413 NXP Semiconductors MPT612 User manual Table 59. Pin description …continued Symbol Type Description PIO26/AD7 PIO26: general purpose input/output digital pin AD7: ADC 0, input 7 PIO27/TRST PIO27: general purpose input/output digital pin TRST: test reset for JTAG interface. If JTAGSEL is HIGH, this pin is automatically configured for use with EmbeddedICE (Debug mode).
Page 61 UM10413 NXP Semiconductors MPT612 User manual  3.0 V) pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and 5 V tolerant (if V and V DD(IO) DD(ADC) analog input function. If configured for an input function, this pad utilizes a built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital section of the pad is disabled.
Page 62: Pin Connect Block
12.1 Features The pin connect block allows individual pin configuration. 12.2 Applications The purpose of the pin connect block is to configure the MPT612 pins to the desired functions. 12.3 Description The pin connect block allows selected pins of the MPT612 to have more than one function.
Page 63 UM10413 NXP Semiconductors MPT612 User manual Table 61. Pin function select register 0 (PINSEL0 - address 0xE002 C000) PINSEL0 Pin name Value Function Value after reset PIO0 GPIO pin 0 TXD0 (UART0) MAT3.1(Timer 3) reserved PIO1 GPIO pin 1 RXD0 (UART0) MAT3.2 (Timer 3)
Page 64: Pin Function Select Register 1 (Pinsel1 - 0Xe002 C004)
UM10413 NXP Semiconductors MPT612 User manual Table 61. Pin function select register 0 (PINSEL0 - address 0xE002 C000) …continued PINSEL0 Pin name Value Function Value after reset 23:22 PIO11 GPIO pin 11 CTS1 (UART1) CAP1.1 (Timer 1) 25:24 PIO12 GPIO pin 12 DSR1 (UART1) MAT1.0 (Timer 1)
Page 65 UM10413 NXP Semiconductors MPT612 User manual Table 62. Pin function select register 1 (PINSEL1 - address 0xE002 C004) …continued PINSEL1 Pin Name Value Function Value after reset PIO19 GPIO pin 19 MISO1 (SPI1) MAT1.2 (Timer 1) reserved PIO20 GPIO pin 20 MOSI1 (SPI1) MAT1.3 (Timer 1)
Page 66: Pin Function Select Register Values
UM10413 NXP Semiconductors MPT612 User manual Table 62. Pin function select register 1 (PINSEL1 - address 0xE002 C004) …continued PINSEL1 Pin Name Value Function Value after reset 29:28 PIO30 GPIO pin 30 TDI (JTAG) MAT3.3 (Timer 3) reserved 31:30 PIO31...
Page 67: Applications
Table 66 represent the enhanced GPIO features available on the MPT612. All of these registers are located directly on the local bus of the CPU for the fastest possible read and write timing and are byte, half-word, and word accessible. A mask register allows writing to individual pins of the GPIO port without the overhead of software masking.
Page 68: Gpio Direction Register (Iodir, Io0Dir - 0Xe002 8008; Fiodir, Fio0Dir - 0X3Fff C000)
UM10413 NXP Semiconductors MPT612 User manual Table 65. GPIO register map (slow speed GPIO APB accessible registers) Generic Description Access Reset value PORT0 name address and name IOPIN GPIO pin value register. Current state of GPIO configured pins can 0xE002 8000 always be read from this register, regardless of pin direction.
Page 69: Fast Gpio Mask Register (Fiomask, Fio0Mask - 0X3Fff C010)
UM10413 NXP Semiconductors MPT612 User manual IO0DIR is the slow speed GPIO register, while the enhanced GPIO functions are supported via the register FIO0DIR. Table 67. GPIO Direction register (IO0DIR - address 0xE002 8008) bit description Symbol Value Description Reset value...
Page 70: Gpio Pin Value Register (Iopin, Io0Pin - 0Xe002 8000; Fiopin, Fio0Pin - 0X3Fff C014)
UM10413 NXP Semiconductors MPT612 User manual Table 70. Fast GPIO mask register (FIO0MASK - address 0x3FFF C010) bit description Symbol Value Description Reset value 31:0 FP0xMASK fast GPIO physical pin access control. 0x0000 0000 pin is affected by writes to registers FIOSET, FIOCLR, and FIOPIN. Current state of pin is observable in register FIOPIN.
Page 71: Gpio Output Set Register (Ioset, Io0Set - 0Xe002 8004; Fioset, Fio0Set - 0X3Fff C018)
UM10413 NXP Semiconductors MPT612 User manual Only pins masked with logic 0s in the mask register (see Section 13.4.2 on page 69) are correlated to the current content of the Fast GPIO pin value register. Table 72. GPIO Pin value register (IO0PIN - address 0xE002 8000) bit description...
Page 72: Gpio Output Clear Register (Ioclr, Io0Clr - 0Xe002 800C; Fioclr, Fio0Clr - 0X3Fff C01C)
UM10413 NXP Semiconductors MPT612 User manual Table 75. GPIO output set register (IO0SET - address 0xE002 8004) bit description Symbol Description Reset value 31:0 P0xSET slow GPIO output value set bits. Bit 0 in IO0SET corresponds to PIO0 ... Bit 31 0x0000 0000 in IO0SET corresponds to PIO31.
Page 73: Gpio Usage Notes
UM10413 NXP Semiconductors MPT612 User manual Table 79. Fast GPIO output clear register 0 (FIO0CLR - address 0x3FFF C01C) bit description Symbol Description Reset value 31:0 FP0xCLR fast GPIO output value clear bits. Bit 0 in FIO0CLR corresponds to PIO0 ... Bit 0x0000 0000 31 in FIO0CLR corresponds to PIO31.
Page 74: Example 2: An Immediate Output Of 0S And 1S On A Gpio Port
13.5.4 Output signal frequency considerations when using slow speed GPIO and enhanced GPIO registers The enhanced features of the fast GPIO pins available on this MPT612 make GPIO pins more responsive to code that has the task of controlling them. In particular, software access to a GPIO pin is 3.5 times faster via the fast GPIO registers than it is when a set of...
Page 75 Figure 17 illustrates the above code executed by the MPT612 Flash memory. The PLL generated f = 60 MHz out of external f = 12 MHz. The MAM was fully enabled with CCLK MEMCR = 2 and MEMTIM = 3, and APBDIV = 1 (PCLK = CCLK).
Page 76: Universal Asynchronous Receiver/Transmitter 0 (Uart0)
UM10413 NXP Semiconductors MPT612 User manual aaa-000580 Fig 17. Illustration of the fast and slow GPIO access and output showing a 3.5 increase of the pin output frequency 14. Universal Asynchronous Receiver/Transmitter 0 (UART0) 14.1 Features • 16 byte receive and transmit FIFOs •...
Page 77 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 82: UART0 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...
Page 78: Uart0 Receiver Buffer Register (U0Rbr - 0Xe000 C000, When Dlab = 0, Read Only)
UM10413 NXP Semiconductors MPT612 User manual 14.3.1 UART0 Receiver buffer register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only) The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface.
Page 79: Uart0 Fractional Divider Register (U0Fdr - 0Xe000 C028)
UM10413 NXP Semiconductors MPT612 User manual Table 85: UART0 Divisor latch LSB register (U0DLL - address 0xE000 C000, when DLAB = 1) bit description Symbol Description Reset value UART0 divisor latch LSB register and U0DLM register determine 0x01 baud rate of UART0...
Page 80: Baud Rate Calculation
UM10413 NXP Semiconductors MPT612 User manual • DIVADDVAL< MULVAL The value of U0FDR must not be modified while transmitting/receiving data or data can be lost or corrupted. If register U0FDR value does not comply with these two requests, then the fractional divider output is undefined.
Page 81 UM10413 NXP Semiconductors MPT612 User manual Calculating UART Baud Rate (BR) PCLK, = PCLK/(16 × BR) true is an integer? false DIVADDVAL = 0 MULVAL = 1 = 1.5 = Int(PCLK/(16 × BR × FR Pick another FR from the range [1.1, 1.9] = PCLK/(16 ×...
Page 82: Uart0 Interrupt Enable Register (U0Ier - 0Xe000 C004, When Dlab = 0)
UM10413 NXP Semiconductors MPT612 User manual Table 88. Fractional divider setting look-up table …continued DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.125 1.364 4/11 1.615 8/13 1.857 1.133 2/15 1.375 1.625 1.867 13/15 1.143 1.385 5/13 1.636 7/11 1.875 1.154...
Page 83: Uart0 Interrupt Identification Register (U0Iir - 0Xe000 C008, Read Only)
UM10413 NXP Semiconductors MPT612 User manual Table 89. UART0 Interrupt enable register (U0IER - address 0xE000 C004, when DLAB = 0) bit description …continued Symbol Value Description Reset value RX Line U0IER[2] enables the UART0 Rx line status interrupts. Status Status of interrupt can be read from U0LSR[4:1].
Page 84 UM10413 NXP Semiconductors MPT612 User manual Table 90: UART0 Interrupt identification register (UOIIR - address 0xE000 C008, read only) bit description …continued Symbol Value Description Reset value ABEOInt end of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
Page 85: Uart0 Fifo Control Register (U0Fcr - 0Xe000 C008)
UM10413 NXP Semiconductors MPT612 User manual Table 91: UART0 interrupt handling …continued U0IIR[3:0] Priority Interrupt type Interrupt source Interrupt reset value 0100 second Rx data available Rx data available or trigger level reached in FIFO U0RBR read (U0FCR0 = 1)
Page 86: Uart0 Line Control Register (U0Lcr - 0Xe000 C00C)
UM10413 NXP Semiconductors MPT612 User manual Table 92. UART0 FIFO Control register (U0FCR - address 0xE000 C008) bit description Bit Symbol Value Description Reset value FIFO Enable 0 UART0 FIFOs disabled. Must not be used in application. active HIGH enable for both UART0 Rx and Tx FIFOs and U0FCR[7:1] access.
Page 87: Uart0 Line Status Register (U0Lsr - 0Xe000 C014, Read Only)
UM10413 NXP Semiconductors MPT612 User manual 14.3.9 UART0 Line status register (U0LSR - 0xE000 C014, read only) The U0LSR is a read-only register that provides status information on the UART0 Tx and Rx blocks. Table 94: UART0 Line status register (U0LSR - address 0xE000 C014, read only) bit description...
Page 88: Uart0 Scratch Pad Register (U0Scr - 0Xe000 C01C)
UM10413 NXP Semiconductors MPT612 User manual Table 94: UART0 Line status register (U0LSR - address 0xE000 C014, read only) bit description …continued Bit Symbol Value Description Reset value Error in RX U0LSR[7] is set when a character with Rx error such as framing error, parity FIFO error or break interrupt, is loaded into U0RBR.
Page 89: Auto-Baud
 14.3.13 UART0 Transmit enable register (U0TER - 0xE000 C030) MPT612’s U0TER enables implementation of software flow control. When TXEn = 1, the UART0 transmitter sends data as long as it is available. When TXEn = 0, UART0 transmission stops.
Page 90: Auto-Baud Modes
UM10413 NXP Semiconductors MPT612 User manual Table 97: UART0 Transmit enable register (U0TER - address 0xE000 C030) bit description Symbol Description Reset value reserved, user software must not write logic 1s to reserved bits; value read from a reserved bit is not defined...
Page 91: Architecture
UM10413 NXP Semiconductors MPT612 User manual 'A' (0x41) or 'a' (0x61) start bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 parity stop UART0 RX start bit LSB of 'A' or 'a' U0ACR start rate counter 16xbaud_rate 16 cycles 16 cycles aaa-000636 a.
Page 92 UM10413 NXP Semiconductors MPT612 User manual The UART0 Baud Rate Generator block, U0BRG, generates the timing enables used by the UART0 TX block. The U0BRG clock input source is the APB clock (PCLK). The main clock is divided down per the divisor specified in registers U0DLL and U0DLM and is a 16...
Page 93 UM10413 NXP Semiconductors MPT612 User manual U0TX NTXRDY TXD0 U0THR U0TSR U0BRG U0DLL NBAUDOUT U0DLM RCLK U0RX NRXRDY INTERRUPT RXD0 U0RBR U0RSR U0IER U0INTR U0IIR U0FCR U0LSR U0SCR U0LCR PA[2:0] PSEL PSTB PWRITE DDIS PD[7:0] INTERFACE PCLK aaa-000583 Fig 20. UART0 block diagram UM10413 All information provided in this document is subject to legal disclaimers.
Page 94: Universal Asynchronous Receiver/Transmitter 1 (Uart1)
UM10413 NXP Semiconductors MPT612 User manual 15. Universal Asynchronous Receiver/Transmitter 1 (UART1) 15.1 Features • UART1 is identical to UART0 with the addition of a modem interface • UART1 contains 16 byte receive and transmit FIFOs • Register locations conform to ‘550 industry standard •...
Page 95 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 99. UART1 register map Name Description Bit functions and addresses Access Reset Address value BIT7 BIT6...
Page 96 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 99. UART1 register map …continued Name Description Bit functions and addresses Access Reset Address value U1FDR Fractional Divider register...
Page 97: Uart1 Receiver Buffer Register (U1Rbr - 0Xe001 0000, When Dlab = 0 Read Only)
UM10413 NXP Semiconductors MPT612 User manual 15.3.1 UART1 Receiver buffer register (U1RBR - 0xE001 0000, when DLAB = 0 read only) The U1RBR is the top byte of the UART1 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface.
Page 98: Uart1 Fractional Divider Register (U1Fdr - 0Xe001 0028)
UM10413 NXP Semiconductors MPT612 User manual Table 102. UART1 Divisor latch LSB register (U1DLL - address 0xE001 0000, when DLAB = 1) bit description Symbol Description Reset value DLLSB UART1 divisor latch LSB register and U1DLM register 0x01 determines baud rate of UART1 Table 103.
Page 99: Baud Rate Calculation
UM10413 NXP Semiconductors MPT612 User manual The value of the U1FDR must not be modified while transmitting/receiving data or data can be lost or corrupted. If register U1FDR value does not comply to these two requests, then the fractional divider output is undefined.
Page 100: Uart1 Interrupt Enable Register (U1Ier - 0Xe001 0004, When Dlab = 0)
UM10413 NXP Semiconductors MPT612 User manual Table 105. Fractional divider setting look-up table DivAddVal/ DivAddVal/ DivAddVal/ DivAddVal/ MulVal MulVal MulVal MulVal 1.000 1.250 1.500 1.750 1.067 1/15 1.267 4/15 1.533 8/15 1.769 10/13 1.071 1/14 1.273 3/11 1.538 7/13 1.778 1.077...
Page 101 UM10413 NXP Semiconductors MPT612 User manual Table 106. UART1 Interrupt enable register (U1IER - address 0xE001 0004, when DLAB = 0) bit description Symbol Value Description Reset value U1IER[0] enables receive data available interrupt Interrupt for UART1. It also controls character receive Enable time-out interrupt.
Page 102: Uart1 Interrupt Identification Register (U1Iir - 0Xe001 0008, Read Only)
UM10413 NXP Semiconductors MPT612 User manual 15.3.6 UART1 Interrupt identification register (U1IIR - 0xE001 0008, read only) The U1IIR provides a status code that denotes the priority and source of a pending interrupt. The interrupts are frozen during an U1IIR access. If an interrupt occurs during an U1IIR access, the interrupt is recorded for the next U1IIR access.
Page 103 U1IIR occurs and the THRE is the highest interrupt (U1IIR[3:1] = 001). The modem interrupt (U1IIR[3:1] = 000) is available in MPT612. It is the lowest priority interrupt and is activated whenever there is any state change on modem inputs pins, DCD, DSR or CTS.
Page 104: Uart1 Fifo Control Register (U1Fcr - 0Xe001 0008)
UM10413 NXP Semiconductors MPT612 User manual 15.3.7 UART1 FIFO control register (U1FCR - 0xE001 0008) The U1FCR controls the operation of the UART1 Rx and Tx FIFOs. Table 109. UART1 FIFO control register (U1FCR - address 0xE001 0008) bit description...
Page 105: Uart1 Modem Control Register (U1Mcr - 0Xe001 0010)
UM10413 NXP Semiconductors MPT612 User manual Table 110. UART1 Line control register (U1LCR - address 0xE001 000C) bit description …continued Symbol Value Description Reset value Break Control disable break transmission enable break transmission. Output pin UART1 TXD forced to logic 0 when U1LCR[6] is active HIGH.
Page 106 UM10413 NXP Semiconductors MPT612 User manual When the receiver FIFO level reaches the programmed trigger level, RTS1 is deasserted (to a high value). It is possible that the sending UART sends an additional byte after reaching the trigger level (assuming sending UART has another byte to send) because it may not recognize the deassertion of RTS1 until after it has begun sending the additional byte.
Page 107: Uart1 Line Status Register (U1Lsr - 0Xe001 0014, Read Only)
UM10413 NXP Semiconductors MPT612 User manual Table 112. Modem status interrupt generation …continued Enable modem CTSen CTS interrupt Delta CTS Delta DCD or Modem status status interrupt (U1MCR[7]) enable (U1MSR[0]) trailing edge RI or interrupt (U1IER[3]) (U1IER[7]) Delta DSR (U1MSR[3] or U1MSR[2] or (U1MSR[1])) The auto-CTS function reduces interrupts to the host system.
Page 108: Uart1 Modem Status Register (U1Msr - 0Xe001 0018)
UM10413 NXP Semiconductors MPT612 User manual Table 113. UART1 Line status register (U1LSR - address 0xE001 0014, read only) bit description …continued Bit Symbol Value Description Reset value Parity Error when parity bit of received character is the wrong state, a parity error occurs. An (PE) U1LSR read clears U1LSR[2].
Page 109: Uart1 Scratch Pad Register (U1Scr - 0Xe001 001C)
UM10413 NXP Semiconductors MPT612 User manual Table 114. UART1 Modem status register (U1MSR - address 0xE001 0018) bit description Bit Symbol Value Description Reset value Delta CTS set on state change of input CTS. Cleared on U1MSR read. no change detected on modem input, CTS...
Page 110: Auto-Baud
UM10413 NXP Semiconductors MPT612 User manual Table 116. Auto-baud control register (U1ACR - address 0xE001 0020) bit description Symbol Value Description Reset value AutoRestart 0 no restart restart in case of time-out (counter restarts at next UART1 Rx falling edge) reserved, user software must not write logic 1s to reserved bits;...
Page 111: Auto-Baud Modes
UM10413 NXP Semiconductors MPT612 User manual to registers U1DLM and U1DLL must be done before register U1ACR write. The minimum and the maximum baud rates supported by UART1 are function of PCLK, number of data bits, stop-bits and parity bits.
Page 112: Uart1 Transmit Enable Register (U1Ter - 0Xe001 0030)
Fig 24. Auto-baud mode 0 and mode 1 waveforms 15.3.16 UART1 Transmit enable register (U1TER - 0xE001 0030) MPT612’s U1TER enables implementation of software and hardware flow control. When TXEn = 1, UART1 transmitter sends data as long as it is available. When bit TXEn is logic 0, UART1 transmission stops.
Page 113: Architecture
UM10413 NXP Semiconductors MPT612 User manual Table 117. UART1 Transmit enable register (U1TER - address 0xE001 0030) bit description Symbol Description Reset value reserved, user software must not write logic 1s to reserved bits; value read from a reserved bit is not defined...
Page 114: I 2 C Interfaces I
UM10413 NXP Semiconductors MPT612 User manual MODEM U1TX NTXRDY TXD1 U1THR U1TSR U1MSR U1BRG U1DLL NBAUDOUT U1MCR U1DLM RCLK U1RX NRXRDY INTERRUPT RXD1 U1RBR U1RSR U1IER U1INTR U1IIR U1FCR U1LSR U1SCR U1LCR PA[2:0] PSEL PSTB PWRITE DDIS PD[7:0] INTERFACE PCLK aaa-000588 Fig 25.
Page 115: Applications
The I C interfaces comply with the entire I C specification, supporting the ability to turn off power to the MPT612 without interfering with other devices on the same I C-bus. UM10413 All information provided in this document is subject to legal disclaimers.
Page 116: Pin Description
UM10413 NXP Semiconductors MPT612 User manual pull-up pull-up resistor resistor C-bus OTHER DEVICE WITH OTHER DEVICE WITH MPT612 INTERFACE INTERFACE aaa-000589 Fig 26. I C-bus configuration 16.4 Pin description Table 118. I C pin description Type Description SDA0,1 input/output C serial data...
Page 117: Master Receiver Mode
UM10413 NXP Semiconductors MPT612 User manual transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. The I C interface enters master transmitter mode when software sets bit STA.
Page 118: Slave Receiver Mode
UM10413 NXP Semiconductors MPT612 User manual SLAVE ADDRESS DATA DATA “0” - Write “1” - Read data transferred (n bytes + Acknowledge) A = Acknowledge (SDA LOW) From Master to Slave A = Not acknowledge (SDA HIGH) From Slave to Master...
Page 119: Slave Transmitter Mode
If one of these addresses is detected, an interrupt is requested. When the MPT612 wants to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted.
Page 120 UM10413 NXP Semiconductors MPT612 User manual ADDRESS REGISTER I2ADR COMPARATOR INPUT FILTER OUTPUT SHIFT REGISTER STAGE I2DAT BIT COUNTER/ ARBITRATION & SYNC LOGIC PCLK INPUT TIMING & FILTER CONTROL LOGIC interrupt OUTPUT SERIAL CLOCK STAGE GENERATOR I2CONSET CONTROL REGISTER & SCL DUTY...
Page 121: Address Register, I2Addr
UM10413 NXP Semiconductors MPT612 User manual 16.6.2 Address register, I2ADDR This register can be loaded with the 7-bit slave address (7 most significant bits) to which the I C block responds when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable general call address (0x00) recognition.
Page 122: Serial Clock Generator
UM10413 NXP Semiconductors MPT612 User manual The synchronization logic synchronizes the serial clock generator with the clock pulses on the SCL line from another device. If two or more master devices generate clock pulses, the “mark” duration is determined by the device that generates the shortest “marks,” and the “space”...
Page 123: Status Decoder And Status Register
UM10413 NXP Semiconductors MPT612 User manual The contents of the I C control register can be read as I2CONSET. Writing to I2CONSET sets bits in the I C control register that correspond to logic 1s in the value written. Conversely, writing to I2CONCLR clears bits in I C control register that correspond to 1s in the value written.
Page 124: C Control Set Register (I2Conset: I2C0, I2C0Conset - 0Xe001 C000 And I2C1, I2C1Conset - 0Xe005 C000)
UM10413 NXP Semiconductors MPT612 User manual 16.7.1 I C Control set register (I2CONSET: I2C0, I2C0CONSET - 0xE001 C000 and I2C1, I2C1CONSET - 0xE005 C000) The I2CONSET registers control setting of bits in register I2CON that controls operation of the I C interface.
Page 125: C Control Clear Register (I2Conclr: I2C0, I2C0Conclr - 0Xe001 C018 And I2C1, I2C1Conclr - 0Xe005 C018)
UM10413 NXP Semiconductors MPT612 User manual STO is the Stop flag. Setting this bit causes the I C interface to transmit a Stop condition in master mode, or recover from an error condition in slave mode. When STO is logic 1 in master mode, a Stop condition is transmitted on the I C-bus.
Page 126: I 2 C Status Register (I2Stat: I2C0, I2C0Stat - 0Xe001 C004 And I2C1, I2C1Stat - 0Xe005 C004)
UM10413 NXP Semiconductors MPT612 User manual Table 123. I C Control set register (I2CONCLR: I2C0, I2C0CONCLR - address 0xE001 C018 and I2C1, I2C1CONCLR - address 0xE005 C018) bit description …continued Bit Symbol Description Reset value STAC start flag clear bit...
Page 127: C Slave Address Register (I2Adr: I2C0, I2C0Adr - 0Xe001 C00C And I2C1, I2C1Adr - Address 0Xe005 C00C)
UM10413 NXP Semiconductors MPT612 User manual 16.7.5 I C Slave address register (I2ADR: I2C0, I2C0ADR - 0xE001 C00C and I2C1, I2C1ADR - address 0xE005 C00C) These registers are readable and writable, and are only used when an I C interface is set to slave mode.
Page 128: Details Of I C Operating Modes
UM10413 NXP Semiconductors MPT612 User manual Table 129. Example of I C clock rates I2SCLL + C Bit frequency (kHz) at PCLK (MHz) I2SCLH 6.25 31.25 62.5 12.5 1.25 6.25 12.5 16.8 Details of I C operating modes The four operating modes are: •...
Page 129: Master Transmitter Mode
UM10413 NXP Semiconductors MPT612 User manual 16.8.1 Master transmitter mode In the master transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 35 on page 131). Before the master transmitter mode can be entered, I2CON must be initialized as follows: Table 131.
Page 130 UM10413 NXP Semiconductors MPT612 User manual Table 132. I2C0ADR and I2C1ADR usage in slave receiver mode Bit: Symbol: own slave 7-bit address The upper 7 bits are the address to which the I C block responds when addressed by a master.
Page 131 UM10413 NXP Semiconductors MPT612 User manual Successful transmission DATA to a Slave Receiver Next transfer started with a Repeated Start condition Acknowledge received after the Slave Address To Master receive mode, entry = MR Acknowledge received after a Data byte...
Page 132 UM10413 NXP Semiconductors MPT612 User manual Successful transmission DATA DATA to a Slave Transmitter Next transfer started with a Repeated Start condition Acknowledge received after the Slave Address To Master transmit mode, entry = MT Arbitration lost in Slave Other Master...
Page 133 UM10413 NXP Semiconductors MPT612 User manual Reception of the own P OR Slave Address and DATA DATA one or more Data bytes are all acknowledged Last data byte P OR received is Not Acknowledged Arbitration lost as Master and addressed as...
Page 134: Slave Transmitter Mode
UM10413 NXP Semiconductors MPT612 User manual Reception of the own P OR Slave Address and DATA DATA one or more Data bytes are all Acknowledged Arbitration lost as Master and addressed as Slave Last data byte transmitted P OR Switched to Not...
Page 135 UM10413 NXP Semiconductors MPT612 User manual Table 134. Master transmitter mode Status Status of I C-bus Application software response Next action taken by I C hardware code and hardware To/from I2DAT To I2CON (I2CSTAT) STA STO SI 0x08 a start condition is load SLA+W SLA+W transmitted;...
Page 136 UM10413 NXP Semiconductors MPT612 User manual Table 135. Master receiver mode Status Status of I C-bus Application software response Next action taken by I C hardware code and hardware To/from I2DAT To I2CON (I2CSTAT) STA STO SI 0x08 a start condition is load SLA+R SLA+R transmitted;...
Page 137 UM10413 NXP Semiconductors MPT612 User manual Table 136. Slave receiver mode Status Status of I C-bus Application software response Next action taken by I C hardware code and hardware To/from I2DAT To I2CON (I2CSTAT) STA STO SI 0x60 own SLA+W received;...
Page 138 UM10413 NXP Semiconductors MPT612 User manual Table 136. Slave receiver mode …continued Status Status of I C-bus Application software response Next action taken by I C hardware code and hardware To/from I2DAT To I2CON (I2CSTAT) STA STO SI 0x98 previously addressed read data byte or switched to not-addressed SLV mode;...
Page 139: Miscellaneous States
UM10413 NXP Semiconductors MPT612 User manual Table 137. Slave transmitter mode Status Status of I C-bus Application software response Next action taken by I C hardware code and hardware To/from I2DAT To I2CON (I2CSTAT) STA STO SI 0xA8 own SLA+R received;...
Page 140: I2Stat = 0Xf8
UM10413 NXP Semiconductors MPT612 User manual 16.8.6 I2STAT = 0xF8 This status code indicates that no relevant information is available because the serial interrupt flag, SI, is not yet set. This occurs between other states and when the I C block is not involved in a serial transfer.
Page 141: Some Special Cases
UM10413 NXP Semiconductors MPT612 User manual Table 138. Miscellaneous states Status Status of I C-bus Application software response Next action taken by I C hardware code and hardware To/from I2DAT To I2CON (I2CSTAT) STA STO SI 0xF8 no relevant state...
Page 142: C-Bus Obstructed By A Low Level On Scl Or Sda
UM10413 NXP Semiconductors MPT612 User manual is achieved by setting the STO flag while the STA flag is still set. No Stop condition is transmitted. The I C hardware behaves as if a Stop condition was received and is able to transmit a Start condition.
Page 143: C State Service Routines
UM10413 NXP Semiconductors MPT612 User manual time limit STA flag STO flag SDA line SCL line start condition aaa-000603 Fig 40. Forced access to a busy I C-bus STA flag SDA line SCL line start condition aaa-000604 (1) Unsuccessful attempt to send a Start condition.
Page 144: I 2 C Interrupt Service
UM10413 NXP Semiconductors MPT612 User manual The I C hardware now begins checking the I C-bus for its own slave address and general call. If the general call or the own slave address is detected, an interrupt is requested and I2STAT is loaded with the appropriate state information.
Page 145: I 2 C Interrupt Routine
UM10413 NXP Semiconductors MPT612 User manual 3. Write 0x20 to I2CONSET to set bit STA. 4. Set up the master receive buffer. 5. Initialize the master data counter to match the length of the message to be received. 6. Exit.
Page 146: Master Transmitter States
UM10413 NXP Semiconductors MPT612 User manual 7. Exit. 16.9.6 Master transmitter states 16.9.6.1 State: 0x18 Previous state was state 8 or state 10, slave address + write is transmitted, ACK is received. The first data byte is transmitted, an ACK bit is received.
Page 147: Master Receive States
UM10413 NXP Semiconductors MPT612 User manual 1. Write 0x24 to I2CONSET to set the STA and AA bits. 2. Write 0x08 to I2CONCLR to clear the SI flag. 3. Exit. 16.9.7 Master receive states 16.9.7.1 State: 0x40 Previous state was state 08 or state 10. Slave address + read is transmitted, ACK is received.
Page 148: Slave Receiver States
UM10413 NXP Semiconductors MPT612 User manual 16.9.8 Slave receiver states 16.9.8.1 State: 0x60 Own slave address + write is received, ACK is returned. Data is received and ACK returned. 1. Write 0x04 to I2CONSET to set bit AA. 2. Write 0x08 to I2CONCLR to clear the SI flag.
Page 149: State: 0X88
UM10413 NXP Semiconductors MPT612 User manual 1. Read data byte from I2DAT into the slave receive buffer. 2. Decrement the slave data counter, skip to step 5 if not the last data byte. 3. Write 0x0C to I2CONCLR to clear the SI flag and bit AA.
Page 150: State: 0Xb0
UM10413 NXP Semiconductors MPT612 User manual 1. Load I2DAT from slave transmit buffer with first data byte. 2. Write 0x04 to I2CONSET to set bit AA. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Set up slave transmit mode data buffer.
Page 151: Spi Interface Spi0
UM10413 NXP Semiconductors MPT612 User manual 17. SPI Interface SPI0 17.1 Features • Single complete and independent SPI controller • Compliant with Serial Peripheral Interface (SPI) specification • Synchronous, serial, full duplex communication • SPI master only • Maximum data bit rate of one eighth of the input clock rate •...
Page 152 UM10413 NXP Semiconductors MPT612 User manual SCK (CPOL = 0) SCK (CPOL = 1) SSEL CPHA = 0 Cycle # CPHA = 0 MOSI (CPHA = 0) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7...
Page 153: General Information
UM10413 NXP Semiconductors MPT612 User manual When a device is a slave, and CPHA is set to logic 0, the transfer starts when the SSEL signal is active, and ends when SSEL is inactive. When a device is a slave, and CPHA is set to logic 1, the transfer starts on the first clock edge when the slave is selected, and ends on the last clock edge where data is sampled.
Page 154: Exception Conditions
UM10413 NXP Semiconductors MPT612 User manual Remark: In order to clear the SPIF status bit, a read or write of the SPI data register is required. Therefore, if the optional read of the SPI data register does not take place, a write to this register is required in order to clear the SPIF status bit.
Page 155: Pin Description
This signal is not directly driven by the master. It can be driven by a simple general-purpose I/O under software control. On pin MPT612, SSEL0 can be used for a different function when the SPI0 interface is only used in Master mode. For example, the pin hosting the SSEL0 function can be configured as an output digital GPIO pin or used to select one of the match outputs.
Page 156 UM10413 NXP Semiconductors MPT612 User manual Table 142: SPI Control register (S0SPCR - address 0xE002 0000) bit description Symbol Value Description Reset value reserved, user software must not write logic 1s to reserved bits; value read from a reserved bit is not...
Page 157: Spi Status Register (S0Spsr - 0Xe002 0004)
UM10413 NXP Semiconductors MPT612 User manual 17.4.2 SPI Status register (S0SPSR - 0xE002 0004) Register S0SPSR controls the operation of the SPI0 as per the configuration bits setting. Table 143: SPI Status register (S0SPSR - address 0xE002 0004) bit description...
Page 158: Spi Interrupt Register (S0Spint - 0Xe002 001C)
UM10413 NXP Semiconductors MPT612 User manual The SPI0 rate can be calculated as: PCLK / SPCCR0 value. The PCLK rate is CCLK / APB divider rate as determined by register APBDIV contents. 17.4.5 SPI Interrupt register (S0SPINT - 0xE002 001C) This register contains the interrupt flag for the SPI0 interface.
Page 159: Spi/Ssp Interface Spi1
UM10413 NXP Semiconductors MPT612 User manual 18. SPI/SSP interface SPI1 18.1 Features • Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive •...
Page 160: Bus Description
UM10413 NXP Semiconductors MPT612 User manual Table 147. SSP pin descriptions …continued Interface pin name/function Pin Name Type Pin description Microwire SSEL1 SSEL Slave Select/Frame Sync/Chip Select. If the SSP is a bus master, it drives this signal shortly before the start of serial data to shortly after the end of serial data, to signify a data transfer as appropriate for the selected bus and mode.
Page 161: Spi Frame Format
UM10413 NXP Semiconductors MPT612 User manual DX/DR 4 to16 bits aaa-000638 a. Single frame transfer DX/DR 4 to16 bits 4 to16 bits aaa-000607 b. Continuous/back-to-back two frames transfer Fig 44. Texas Instruments synchronous serial frame format For a device configured as a master in this mode, CLK and FS are forced LOW, and the transmit data line DX is tri-stated whenever the SSP is idle.
Page 162: Spi Format With Cpol = 0, Cpha = 0
UM10413 NXP Semiconductors MPT612 User manual The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.
Page 163: Spi Format With Cpol = 0, Cpha = 1
UM10413 NXP Semiconductors MPT612 User manual The data is now captured on the rising and propagated on the falling edges of the SCK signal. If a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit is captured.
Page 164: Spi Format With Cpol = 1, Cpha = 0
UM10413 NXP Semiconductors MPT612 User manual 18.3.6 SPI format with CPOL = 1, CPHA = 0 Single and continuous transmission signal sequences for SPI format with CPOL = 1, CPHA = 0 are shown in Figure SSEL MOSI MISO 4 to 16 bits aaa-000567 a.
Page 165: Spi Format With Cpol = 1, Cpha = 1
UM10413 NXP Semiconductors MPT612 User manual However, in the case of continuous back-to-back transmissions, the SSEL signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if bit CPHA is logic 0.
Page 166 UM10413 NXP Semiconductors MPT612 User manual 8 bit control 4 to 16 bits output data aaa-000612 Fig 49. Microwire frame format (single transfer) Microwire format is similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSP to the off-chip slave device.
Page 167: Setup And Hold Time Requirements On Cs With Respect To Sk In Microwire Mode
UM10413 NXP Semiconductors MPT612 User manual 8 bit control 4 to 16 bits 4 to 16 bits output data output data aaa-000613 Fig 50. Microwire frame format (continuous transfers) 18.3.9 Setup and hold time requirements on CS with respect to SK in Microwire...
Page 168: (Sspcr0 - 0Xe006 8000)
UM10413 NXP Semiconductors MPT612 User manual Table 148. SSP register map …continued Name Description Access Reset value Address SSPSR status register 0x03 0xE006 800C SSPCPSR clock prescale register 0x00 0xE006 8010 SSPIMSC interrupt mask set and clear register 0x00 0xE006 8014...
Page 169: (Sspcr1 - 0Xe006 8004)
UM10413 NXP Semiconductors MPT612 User manual Table 149. SSP Control register 0 (SSPCR0 - address 0xE006 8000) bit description …continued Symbol Value Description Reset value CPHA clock out phase. Only used in SPI mode. SSP controller captures serial data on the first clock transition of frame, that is, the transition away from the inter-frame state of the clock line.
Page 170: Ssp Status Register (Sspsr - 0Xe006 800C)
UM10413 NXP Semiconductors MPT612 User manual Table 151: SSP Data register (SSPDR - address 0xE006 8008) bit description Symbol Description Reset value 15:0 DATA write: software can write data to be sent in a future frame to this 0x0000 register whenever bit TNF in the status register is logic 1, indicating that Tx FIFO is not full.
Page 171: Ssp Interrupt Mask Set/Clear Register (Sspimsc - 0Xe006 8014)
UM10413 NXP Semiconductors MPT612 User manual 18.4.6 SSP Interrupt mask set/clear register (SSPIMSC - 0xE006 8014) This register controls whether either of the four possible interrupt conditions in the SSP controller are enabled. Note that ARM uses the word “masked” in the opposite sense from classic computer terminology, in which “masked”...
Page 172: Ssp Interrupt Clear Register (Sspicr - 0Xe006 8020)
UM10413 NXP Semiconductors MPT612 User manual Table 156: SSP Masked interrupt status register (SSPMIS - address 0xE006 801C) bit description Symbol Description Reset value RORMIS logic 1 if another frame was received while Rx FIFO was full, and this interrupt is enabled...
Page 173: Pin Description
UM10413 NXP Semiconductors MPT612 User manual 19.3 Pin description Table 158 gives a brief summary of each of ADC-related pin. Table 158. ADC pin description Type Description AD7:0 input analog inputs. The ADC cell can measure the voltage on any of these input signals.
Page 174: A/D Control Register (Ad0Cr - 0Xe003 4000)
UM10413 NXP Semiconductors MPT612 User manual Reset value reflects the data stored in used bits only. It does not include the content of reserved bits. 19.4.1 A/D Control register (AD0CR - 0xE003 4000) Table 160: A/D Control register (AD0CR - address 0xE003 4000) bit description...
Page 175: A/D Global Data Register (Ad0Gdr - 0Xe003 4004)
UM10413 NXP Semiconductors MPT612 User manual Table 160: A/D Control register (AD0CR - address 0xE003 4000) bit description …continued Symbol Value Description Reset value 26:24 START if bit BURST is logic 0, these bits control whether and when an A/D conversion is...
Page 176: A/D Interrupt Enable Register (Ad0Inten - 0Xe003 400C)
UM10413 NXP Semiconductors MPT612 User manual Table 162: A/D Status register (AD0STAT - address 0xE003 4030) bit description Symbol Description Reset value reserved, user software must not write logic 1s to reserved bits; value read from a reserved bit is not defined...
Page 177: A/D Data Registers (Ad0Dr0 To Ad0Dr7 - 0Xe003 4010 To 0Xe003 402C)
UM10413 NXP Semiconductors MPT612 User manual Table 163. A/D Interrupt enable register (AD0INTEN - address 0xE003 400C) bit description …continued Symbol Value Description Reset value ADGINTEN only the individual ADC channels enabled by ADINTEN7:0 generates interrupts 1 only the global DONE flag in ADDR is enabled to generate an interrupt 31:9 reserved, user software must not write logic 1s to reserved bits;...
Page 178: Pwm Mosfet Gate Driver Switching Module
Fully programmed through firmware APIs only. No direct register access to the application 20.2 Description MPT612 provides a PWM module, which can be programmed only through the firmware APIs. This module enables the PWM signal to drive the gate driver circuitry with the defined PWM switching frequency.
Page 179: 32-Bit Timers: Timer1
UM10413 NXP Semiconductors MPT612 User manual The maximum PWM duty cycle count calculated in Equation 8 is defined as a 100 % duty cycle. For a PWM signal with 0 % duty cycle, the PWM duty cycle count is 0.
Page 180: Pin Description
UM10413 NXP Semiconductors MPT612 User manual 21.4 Pin description Table 165 gives a brief summary of each of the timer counter related pins. Table 165. Timer counter pin description Type Description CAP1[3..0] input capture signals. A transition on a capture pin can be configured to load one of the capture registers with the value in the timer counter and optionally generate an interrupt.
Page 181: 0Xe000 8000)
UM10413 NXP Semiconductors MPT612 User manual Table 166. Timer counter1 register map …continued Generic Description Access Reset Timer/ name value counter1 address and name match register 0. MR0 can be enabled through MCR to reset TC, stop 0xE000 8018 both TC and PC, and/or generate an interrupt every time MR0 T1MR0 matches TC.
Page 182: Timer Control Register (Tcr, Timer1: T1Tcr - 0Xe000 8004)
UM10413 NXP Semiconductors MPT612 User manual 21.5.2 Timer control register (TCR, TIMER1: T1TCR - 0xE000 8004) The timer control register (TCR) is used to control the operation of the timer counter. Table 168: Timer control register (TCR, TIMER1: T1TCR - address 0xE000 8004) bit...
Page 183: Timer Counter (Tc, Timer1: T1Tc - 0Xe000 8008)
UM10413 NXP Semiconductors MPT612 User manual Table 169: Count control register (CTCR, TIMER1: T1TCR - address 0xE000 8070) bit description …continued Symbol Value Description Reset value Count if bits 1:0 in this register are not 00, these bits select which...
Page 184: Capture Registers (Cr0 - Cr3)
UM10413 NXP Semiconductors MPT612 User manual Table 170: Match control register (MCR, TIMER1: T1MCR - address 0xE000 8014) bit description Symbol Value Description Reset value MR0I interrupt on MR0: an interrupt is generated when MR0 matches the value in TC...
Page 185: External Match Register (Emr, Timer1: T1Emr - 0Xe000 803C)
UM10413 NXP Semiconductors MPT612 User manual Table 171: Capture control register (CCR, TIMER1: T1CCR - address 0xE000 8028) bit description Symbol Value Description Reset value CAP0RE 1 capture on CAPn.0 rising edge: a sequence of 0s then 1s on CAPn.0 causes CR0 to be...
Page 186: Pwm Control Register (Pwmcon, Timer1: Pwm1Con - 0Xe000 8074)
UM10413 NXP Semiconductors MPT612 User manual Table 172: External match register (EMR, TIMER1: T1EMR - address 0xE000 803C) bit description Symbol Description Reset value external match 0. Reflects the state of output MAT1.0, whether this output is connected to its pin. If a match occurs between TC and MR0, this output of the timer can either toggle, go LOW, go HIGH, or do nothing.
Page 187: Rules For Single Edge-Controlled Pwm Outputs
UM10413 NXP Semiconductors MPT612 User manual Table 174: PWM Control register (PWMCON, TIMER1: PWM1CON - address 0xE000 8074) bit description Symbol Description Reset value PWM enable if logic 1, PWM mode is enabled for MATn.0. If logic 0, MATn.0 is controlled by EM0 PWM enable if logic 1, PWM mode is enabled for MATn.1.
Page 188: Example Timer Operation
UM10413 NXP Semiconductors MPT612 User manual PWM2/MAT2 MR2 = 100 PWM1/MAT1 MR1 = 41 PWM0/MAT0 MR0 = 65 (counter is reset) aaa-000615 Fig 52. Sample PWM waveforms with a PWM cycle length of 100 (selected by MR3) and MAT3:0 enabled as PWM outputs by register PWCON 21.6 Example timer operation...
Page 189: Architecture
UM10413 NXP Semiconductors MPT612 User manual 21.7 Architecture The block diagram for timer counter1 is shown in Figure MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MAT[3:0]...
Page 190: Applications
Due to the limited number of pins on the MPT612, none of the four match outputs of Timer3 are connected to device pins.
Page 191: Register Description
UM10413 NXP Semiconductors MPT612 User manual Table 175. Timer counter pin description Type Description MAT3[3..0] output external match output 0/1. If a match register 0/1 (MR3:0) equals the Timer Counter (TC), this output can either toggle, go LOW, go HIGH, or do nothing.
Page 192: Interrupt Register (Ir Timer3: T3Ir - 0Xe007 4000)
UM10413 NXP Semiconductors MPT612 User manual 22.5.1 Interrupt register (IR TIMER3: T3IR - 0xE007 4000) The interrupt register consists of 4 bits for the match interrupts and 4 bits for the capture interrupts. If an interrupt is generated, the corresponding bit in the IR is HIGH. Otherwise, the bit is LOW.
Page 193: Prescale Register (Pr, Timer3: T3Pr - 0Xe007 400C)
UM10413 NXP Semiconductors MPT612 User manual 22.5.5 Prescale register (PR, TIMER3: T3PR - 0xE007 400C) The 16-bit prescale register specifies the maximum value for the prescale counter. 22.5.6 Prescale counter register (PC, TIMER3: T3PC - 0xE007 4010) The 16-bit prescale counter register controls division of PCLK by some constant value before it is applied to the timer counter.
Page 194: External Match Register (Emr, Timer3: T3Emr - 0Xe007 403C)
UM10413 NXP Semiconductors MPT612 User manual Table 180: Match control register (MCR, TIMER3: T3MCR - address 0xE007 4014) bit description …continued Symbol Value Description Reset value MR3R reset on MR3: TC is reset if MR3 matches it feature disabled MR3S...
Page 195: Pwm Control Register (Pwmcon, Timer3: Pwm3Con - 0Xe007 4074)
UM10413 NXP Semiconductors MPT612 User manual Table 182. External match control EMR[11:10], EMR[9:8], Function EMR[7:6], or EMR[5:4] do nothing clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out) set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out) toggle the corresponding External Match bit/output 22.5.10 PWM Control register (PWMCON, TIMER3: PWM3CON - 0xE007 4074)
Page 196: Example Timer Operation
UM10413 NXP Semiconductors MPT612 User manual • If a match register contains the same value as the timer reset value (the PWM cycle length), then the PWM output is reset to LOW on the next clock tick. Therefore, the PWM output always consists of a one clock tick wide positive pulse with a period determined by the PWM cycle length (that is, the timer reload value).
Page 197: Architecture
UM10413 NXP Semiconductors MPT612 User manual PCLK prescale counter timer counter TCR[0] (counter enable) interrupt aaa-000621 Fig 58. A timer cycle in which PR = 2, MRx = 6, and both interrupt and stop on match are enabled 22.7 Architecture...
Page 198: Watchdog Timer (Wdt)
UM10413 NXP Semiconductors MPT612 User manual MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER INTERRUPT REGISTER CONTROL MATn[3:0] INTERRUPT CAP2[2:0] STOP ON MATCH RESET ON MATCH LOAD[3:0] CAPTURE CONTROL REGISTER...
Page 199: Applications
PCLK 23.2 Applications The purpose of the watchdog is to reset the MPT612 within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog generates a system reset if the user program fails to "feed" (or reload) the watchdog within a predetermined amount of time.
Page 200: Watchdog Mode Register (Wdmod - 0Xe000 0000)
WDRESET enabled. when this mode is selected, a watchdog counter underflow resets the MPT612. While the watchdog interrupt is also enabled in this case (WDEN = 1), it is not recognized since the watchdog reset clears the WDINT flag.
Page 201: Watchdog Timer Constant Register (Wdtc - 0Xe000 0004)
UM10413 NXP Semiconductors MPT612 User manual Table 186: Watchdog mode register (WDMOD - address 0xE000 0000) bit description Symbol Description Reset value WDTOF WDTOF watchdog time-out flag 0 (only after external reset) WDINT WDINT watchdog interrupt flag (read only) reserved, user software must not write logic 1s to reserved bits;...
Page 202: Real-Time Clock (Rtc)
24.1 Introduction References to Deep power-down mode and to control registers PWRCTRL and GPREG0 to GPREG3 only apply to revision A and above of the MPT612. Deep power-down mode is implemented in addition to Idle and Power-down modes; see Section 24.6.14 on page 210.
Page 203: Features
The Real-Time Clock (RTC) is a set of counters for measuring time when system power is on and optionally when it is off. It uses little power in Power-down mode. On the MPT612, the RTC can be clocked by a separate 32.768 kHz oscillator or by a programmable prescale divider based on the APB clock.
Page 204: Pin Description
UM10413 NXP Semiconductors MPT612 User manual 24.5 Pin description Table 190. RTC pin description Name Type Description RTCX1 input to RTC oscillator circuit RTCX2 output from RTC oscillator circuit Remark: If RTC is not used, RTCX1/2 pins can be left floating RTC power supply: Voltage on this pin supplies the power to RTC.
Page 205: Rtc Interrupts
If the RTC is operating from its own oscillator on the RTCX1-2 pins, the RTC interrupt can bring the MPT612 out of Power-down or Deep power-down mode. When the RTC interrupt is enabled for wake-up and its selected event occurs, the oscillator wake-up cycle associated with the X1/2 pins is started.
Page 206: Interrupt Location Register (Ilr - 0Xe002 4000)
UM10413 NXP Semiconductors MPT612 User manual Table 192. Miscellaneous registers Name Size Description Access Address interrupt location. Reading this location 0xE002 4000 indicates source of an interrupt. Writing a logic 1 to the appropriate bit at this location clears associated interrupt.
Page 207: Clock Control Register (Ccr - 0Xe002 4008)
UM10413 NXP Semiconductors MPT612 User manual If the RTC is driven by the external 32.786 kHz oscillator, subsequent read operations of the CTC can yield an incorrect result. The CTC is implemented as a 15-bit ripple counter so that not all 15 bits change simultaneously. The LSB changes first, then the next, and so on.
Page 208: Alarm Mask Register (Amr - 0Xe002 4010)
UM10413 NXP Semiconductors MPT612 User manual 24.6.7 Alarm mask register (AMR - 0xE002 4010) The alarm mask register (AMR) allows the user to mask any of the alarm registers. Table 197 shows the relationship between the bits in the AMR and the alarms. For the alarm function, every non-masked alarm register must match the corresponding time counter for an interrupt to be generated.
Page 209: Consolidated Time Register 1 (Ctime1 - 0Xe002 4018)
UM10413 NXP Semiconductors MPT612 User manual Table 198: Consolidated time register 0 (CTIME0 - address 0xE002 4014) bit description Symbol Description Reset value 23:21 reserved, user software must not write logic 1s to reserved bits; value read from a reserved bit is not defined...
Page 210: Leap Year Calculation
(GPREG[2:0]) remain fully powered up and can be used to store information while the rest of the chip is powered down. The registers are available in newer versions of the MPT612 only; see Section 24.1 “Introduction”...
Page 211: Deep Power-Down Control Register (Pwrctrl - 0Xe002 4040)
UM10413 NXP Semiconductors MPT612 User manual 24.6.15 Deep power-down control register (PWRCTRL - 0xE002 4040) The deep power-down control register controls the power to the main core and either enables or disables the external 32 kHz oscillator and the SRAM block.
Page 212: Rtc Usage Notes
V or an DD(RTC) independent power supply (external battery). If the clock source is lost, interrupted, or altered, no provision is made in the MPT612 to retain RTC status upon the V power DD(RTC) loss, or to maintain time incrementation.
Page 213: Reference Clock Divider (Prescaler)
The reference clock divider consists of a 13-bit integer counter and a 15-bit fractional counter. The reasons for these counter sizes are as follows: 1. For frequencies that are expected to be supported by the MPT612, a 13-bit integer counter is required. This can be calculated as 160 MHz divided by 32,768 minus 1 = 4881 with a remainder of 26,624.
Page 214: Prescaler Fraction Register (Prefrac - 0Xe002 4084)
UM10413 NXP Semiconductors MPT612 User manual Table 207: Prescaler integer register (PREINT - address 0xE002 4080) bit description Symbol Description Reset value 12:0 Prescaler Integer contains integer portion of RTC prescaler value 15:13 reserved, user software must not write logic 1s to reserved bits;...
Page 215: Prescaler Operation
UM10413 NXP Semiconductors MPT612 User manual to clock tick PCLK counter (APB clock) UNDERFLOW 15-BIT FRACTION COUNTER 13-BIT INTEGER COUNTER (DOWN COUNTER) RELOAD COMBINATORIAL LOGIC extend reload 13-BIT RELOAD INTEGER 15-BIT FRACTION REGISTER REGISTER (PREFRAC) (PREINT) APB bus aaa-000625 Fig 62. RTC prescaler block diagram 24.8.4 Prescaler operation...
Page 216: Rtc External 32 Khz Oscillator Component Selection
The RTC external oscillator circuit is shown in Figure 63. Since the feedback resistance is integrated on chip, only a crystal, the capacitances C and C need to be connected externally to the MPT612. MPT612 RTCX1 RTCX2 32 kHz Xtal C x1...
Page 217: Flash Memory System And Programming
27 pF, 27 pF 25. Flash memory system and programming 25.1 Introduction The MPT612 has three levels of Code Read Protection (CRP) implemented: • CRP1: disables access to chip via the JTAG pins and allows partial flash updates (excluding flash sector 0) using a limited set of the ISP commands. This mode is...
Page 218: Memory Map After Any Reset
Remark: Memory regions are not drawn to scale. Fig 64. Map of lower memory after reset for MPT612 with 32 kB of flash memory 25.5.2 Criterion for valid user code Criterion for valid user code: The reserved ARM interrupt vector location (0x0000 0014) must contain the 2’s complement of the check-sum of the remaining interrupt vectors.
Page 219: Communication Protocol
UM10413 NXP Semiconductors MPT612 User manual vectors in sector 0 of the flash. If the signatures match, the execution control is transferred to the user code by loading the program counter with 0x0000 0000. Hence the user flash reset vector must contain a jump instruction to the entry point of the user application code.
Page 220: Isp Flow Control
UM10413 NXP Semiconductors MPT612 User manual 25.5.7 ISP flow control A software XON/XOFF flow control scheme is used to prevent data loss due to buffer overrun. When the data arrives rapidly, the ASCII control character DC3 (stop) is sent to stop the flow of data.
Page 221: Boot Process Flowchart
UM10413 NXP Semiconductors MPT612 User manual 25.5.14 Boot process flowchart RESET INITIALIZE ENABLED? ENABLE DEBUG WATCHDOG FLAG SET? USER CODE Enter ISP VALID? MODE? (PIO14 LOW?) EXECUTE INTERNAL USER CODE RUN AUTO-BAUD AUTO-BAUD SUCCESSFUL? RECEIVE CRYSTAL FREQUENCY RUN ISP COMMAND...
Page 222: Sector Numbers
The boot block is present at addresses 0x7FFF E000 to 0x7FFF FFFF in all devices. ISP and IAP commands do not allow write/erase/go operation on the boot block. The entire 32 kB of flash memory on the MPT612 is available for the user’s application and nxLibMpt firmware.
Page 223: Flash Content Protection Mechanism
0x0000 7000 to 0x0000 7FFF 25.7 Flash content protection mechanism The MPT612 is equipped with the Error Correction Code (ECC) capable flash memory. The purpose of an error correction module is twofold. First, it decodes data words read from the memory into output data words. Second, it encodes data words to be written to the memory.
Page 224 UM10413 NXP Semiconductors MPT612 User manual Table 212. Code read protection options Name Pattern Description programmed in 0x000001FC CRP1 0x12345678 access to chip via the JTAG pins is disabled. This mode allows partial flash update using the following ISP commands and restrictions: •...
Page 225: Isp Commands
UM10413 NXP Semiconductors MPT612 User manual In case a CRP mode is enabled and access to the chip is allowed via the ISP, an unsupported or restricted ISP command is terminated with return code CODE_READ_PROTECTION_ENABLED. 25.9 ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command.
Page 226: Set Baud Rate
UM10413 NXP Semiconductors MPT612 User manual 25.9.2 Set Baud Rate <baud rate> <stop bit> Table 216. ISP Set Baud Rate command Command Input baud rate: 9600 | 19200 | 38400 | 57600 | 115200 | 230400 stop bit: 1 | 2...

Page 227: Read Memory

UM10413 NXP Semiconductors MPT612 User manual the ISP command handler responds with "OK<CR><LF>" to continue further transmission. If the check-sum does not match, the ISP command handler responds with "RESEND<CR><LF>". In response, the host must retransmit the bytes. Table 219. ISP Write to RAM command...

Page 228: Prepare Sector(S) For Write Operation
UM10413 NXP Semiconductors MPT612 User manual 25.9.6 Prepare sector(s) for write operation <start sector number> <end sector number> This command makes flash write/erase operation a two-step process. Table 221. ISP Prepare sector(s) for write operation command Command Input start sector number...

Page 229: Go

UM10413 NXP Semiconductors MPT612 User manual 25.9.8 Go <address> <mode> Table 223. ISP Go command Command Input address: flash or RAM address from which the code execution is to start. This address must be on a word boundary. mode: T (execute program in Thumb mode) | A (execute program in ARM mode)

Page 230: Blank Check Sector(S)
Command Input none Return Code CMD_SUCCESS followed by part identification number in ASCII; see Table 227 Description reads the part identification number Table 227. MPT612 part identification numbers Device ASCII/dec coding Hex coding MPT612 327441 0x0004 FF11 25.9.12 Read boot code version number Table 228.

Page 231: Compare
UM10413 NXP Semiconductors MPT612 User manual 25.9.13 Compare <address1> <address2> <no of bytes> Table 229. ISP Compare command Command Input address1 (DST): starting flash or RAM address of data bytes to be compared. address must be a word boundary. address2 (SRC): starting flash or RAM address of data bytes to be compared.

Page 232: Iap Commands
UM10413 NXP Semiconductors MPT612 User manual Table 230. ISP Return codes summary …continued Return Mnemonic Description code ADDR_NOT_MAPPED address is not mapped in the memory map. Count value is considered where applicable. CMD_LOCKED command is locked INVALID_CODE unlock code is invalid...
Page 233 UM10413 NXP Semiconductors MPT612 User manual iap_entry=(IAP) IAP_LOCATION; The following statement can be used to call IAP: iap_entry (command, result); The IAP call can be simplified further using the symbol definition file feature supported by ARM Linker in ADS (ARM Developer Suite). Assembly code can also be used to call the IAP routine.
Page 234: Prepare Sector(S) For Write Operation
UM10413 NXP Semiconductors MPT612 User manual COMMAND CODE command parameter PARAMETER 1 table PARAMETER 2 ARM REGISTER r0 PARAMETER n ARM REGISTER r1 STATUS CODE RESULT 1 command result table RESULT 2 RESULT n aaa-000629 Fig 67. IAP Parameter passing 25.10.1 Prepare sector(s) for write operation...
Page 235: Copy Ram To Flash
UM10413 NXP Semiconductors MPT612 User manual 25.10.2 Copy RAM to flash Table 233. IAP Copy RAM to flash command Command Copy RAM to flash Input command code: 5110 param0(DST): destination flash address where data bytes are to be written. Address must be a 256 byte boundary.
Page 236: Blank Check Sector(S)
UM10413 NXP Semiconductors MPT612 User manual 25.10.4 Blank check sector(s) Table 235. IAP Blank check sector(s) command Command Blank check sector(s) Input command code: 5310 param0: start sector number param1: end sector number (must be greater than or equal to start sector...
Page 237: Compare
UM10413 NXP Semiconductors MPT612 User manual 25.10.7 Compare <address1> <address2> <no of bytes> Table 238. IAP Compare command Command Compare Input command code: 5610 param0(DST): starting flash or RAM address of data bytes to be compared. Address must be a word boundary.

Page 238: Reinvoke Isp
UM10413 NXP Semiconductors MPT612 User manual 25.10.8 Reinvoke ISP Table 239. Reinvoke ISP Command Compare Input command code: 5710 Return Code none Result none Description invokes the bootloader in ISP mode. Maps boot vectors, configures PIO1 as an input and sets the APB divider register to 0 before entering the ISP mode. This command can be used when a valid user program is present in the internal flash memory and the PIO14 pin is not accessible to force the ISP mode.
Page 239: Embeddedice Logic
UM10413 NXP Semiconductors MPT612 User manual 26. EmbeddedICE logic 26.1 Features • In order to start the debugging session, no target resources are required by the software debugger • Software debugger talks via a JTAG (Joint Test Action Group) port directly to the core •...
Page 240: Pin Description
0072A). Also used during entry into debug mode. 26.5 Reset state of multiplexed pins On the MPT612, pins TMS, TCK, TDI, TDO, and TRST are multiplexed with PIO27 to PIO31. To make them occur as a debug port, JTAGSEL must be held HIGH during and after reset.
Page 241: Register Description
UM10413 NXP Semiconductors MPT612 User manual 26.6 Register description The EmbeddedICE logic contains 16 registers as shown in Table 242. The ARM7TDMI-S debug architecture is described in detail in ARM7TDMI-S (rev 4) Technical Reference Manual (ARM DDI 0234A) published by ARM Limited.
Page 242: Enable Debug Mode
JTAG pins. For the effect of hardware override related to JTAGSEL and RTCK, see Section 11.2 “MPT612 pin description” on page UM10413 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Page 243: Jtag Pin Selection
UM10413 NXP Semiconductors MPT612 User manual wake-up timer count time internal reset JTAGSEL (2)(3) RTCK aaa-000632 (1) JTAGSEL must be HIGH. (2) RTCK must be HIGH asRST is released. An internal pull-up causes RTCK to be HIGH if it is not pulled LOW externally.
Page 244: Description
UM10413 NXP Semiconductors MPT612 User manual 27.3 Description RealMonitor is a lightweight debug monitor that allows interrupts to be serviced while the user debugs his foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic.
Page 245: Rmhost
UM10413 NXP Semiconductors MPT612 User manual DEBUGGER host RDI 1.5.1 REALMONITOR.DLL RMHOST RDI 1.5.1 RT RealMonitor JTAG UNIT protocol DCC transmissions over the JTAG link RMTARGET TARGET BOARD target AND PROCESSOR APPLICATION aaa-000633 Fig 71. RealMonitor components 27.3.2 RMHost RMHost is located between a debugger and a JTAG unit. The RMHost controller, RealMonitor.dll, converts generic Remote Debug Interface (RDI) requests from the...
Page 246 UM10413 NXP Semiconductors MPT612 User manual SWI abort undef stop SWI abort undef RUNNING STOPPED PANIC aaa-000634 Fig 72. RealMonitor as a state machine A debugger such as the ARM eXtended Debugger (AXD) or other RealMonitor aware debugger, that runs on a host computer, can connect to the target to send commands and receive data.
Page 247: How To Enable Realmonitor
UM10413 NXP Semiconductors MPT612 User manual • RealMonitor stops the foreground application. Both IRQs and FIQs continue to be serviced if they were enabled by the application at the time the foreground application was stopped. 27.4 How to enable RealMonitor To enable RealMonitor, the following steps must be performed.
Page 248: Handling Exceptions
UM10413 NXP Semiconductors MPT612 User manual 27.4.9 Handling exceptions This section describes the importance of sharing exception handlers between RealMonitor and the user application. 27.4.10 RealMonitor exception handling To function properly, RealMonitor must be able to intercept certain interrupts and exceptions.
Page 249 UM10413 NXP Semiconductors MPT612 User manual IMPORT rm_prefetchabort_handler IMPORT rm_dataabort_handler IMPORT rm_irqhandler2 IMPORT rm_undef_handler IMPORT User_Entry ;Entry point of user application. CODE32 ENTRY ;Define exception table. Instruct linker to place code at address 0x0000 0000 AREA exception_table, CODE LDR pc, Reset_Address...
Page 250 UM10413 NXP Semiconductors MPT612 User manual sp,r2,#0x5F ; Initialize the IRQ mode stack for RealMonitor and User r1, r0, #0x1f r1, r1, #0x12 CPSR_c, r1 ;Keep 32 bytes for Abort mode stack sp,r2,#0x7F ; Return to the original mode. CPSR_c, r0 ;...
Page 251: Realmonitor Build Options
UM10413 NXP Semiconductors MPT612 User manual cpsr_c,0x1F ;Re-enable IRQ, go to system mode ;User should insert code here if non vectored Interrupt sharing is ;required. Each non vectored shared irq handler must return to ;the interrupted instruction by using the following code.
Page 252 UM10413 NXP Semiconductors MPT612 User manual Enabled for cores with EmbeddedICE-RT. This device uses ARM-7TDMI-S Rev 4 with EmbeddedICE-RT. RM_OPT_SEMIHOSTING=FALSE This option enables or disables support for SWI semi-hosting. Semi-hosting provides code running on an ARM target using facilities on a host computer that is running an ARM debugger.
Page 253: Abbreviations
UM10413 NXP Semiconductors MPT612 User manual RM_OPT_SDM_INFO=FALSE SDM gives additional information about application board and processor-to-debug tools. RM_OPT_MEMORYMAP=FALSE This option determines whether a memory map of the board is built into the target and made available through the capabilities table.
Page 254 UM10413 NXP Semiconductors MPT612 User manual Table 244. Abbreviations …continued Acronym Description SRAM Static Random Access Memory Synchronous Serial Port Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter Vector Interrupt Controller Write Only UM10413 All information provided in this document is subject to legal disclaimers.
Page 255: Legal Information
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards In no event shall NXP Semiconductors, its affiliates or their suppliers be liable customer for the products described herein shall be limited in accordance to customer for any special, indirect, consequential, punitive or incidental with the Terms and conditions of commercial sale of NXP Semiconductors.
Page 256: Tables
MPT612 User manual 30. Tables Table 1. MPT612 device information ....4 15 - 0xFFFF F200 to 23C) bit description ..26 Table 2.
Page 257 UM10413 NXP Semiconductors MPT612 User manual Table 56. Reset source identification register (RSIR - address 0xE000 C000, when DLAB = 0, write address 0xE01F C180) bit description ..54 only) bit description ..... 78 Table 57.
Page 258 UM10413 NXP Semiconductors MPT612 User manual address 0xE001 0008, read only) bit description......127 bit description ......102 Table 129.
Page 259 0xE007 4014) bit description ..193 Table 211. Flash sectors in MPT612 ....223 Table 181: External match register (EMR, TIMER3: T3EMR - Table 212.
Page 260: Figures
31. Figures Fig 1. MPT612 block diagram .....6 Fig 26. I C-bus configuration..... 116 Fig 2.
Page 261 Fig 63. RTC 32 kHz crystal oscillator circuit ..216 Fig 64. Map of lower memory after reset for MPT612 with 32 kB of flash memory ....218 Fig 65.
Page 262: Table Of Contents
Protection enable register (VICProtection - MPT612 memory remapping and boot block . 10 0xFFFF F020) ......27 7.2.1...
Page 263 11.2 MPT612 pin description ....58 when DLAB = 1)..... . . 78 14.3.4...
Page 264 UM10413 NXP Semiconductors MPT612 User manual 14.3.11 UART0 Auto-baud control register 16.4 Pin description ......116 (U0ACR - 0xE000 C020) ....88 16.5...
Page 265 UM10413 NXP Semiconductors MPT612 User manual 16.8.10 Data transfer after loss of arbitration ..141 17.2.1 SPI overview ......151 16.8.11...
Page 266 UM10413 NXP Semiconductors MPT612 User manual 18.4.8 SSP Masked interrupt register 21.5.10 Capture control register (CCR, TIMER1: T1CCR - (SSPMIS - 0xE006 801C)....171 0xE000 8028)......184 18.4.9...
Page 267 UM10413 NXP Semiconductors MPT612 User manual 23.4.4 WatchDog timer value register (WDTV - 25.5.1 Memory map after any reset ... . 218 0xE000 000C)......201 25.5.2...
Page 268 UM10413 NXP Semiconductors MPT612 User manual EmbeddedICE logic ....239 26.1 Features ......239 26.2...
Page 269 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: OM13007,598...

NXP Semiconductors MPT612 User Manual

1 Introduction

2 Features

3 Applications

4 Device Information

5 Architectural Overview

6 Block Diagram

7 Memory Addressing

8 Memory Acceleration Module (MAM)

9 Vectored Interrupt Controller (VIC)

10 System Control Block

11 Pin Configuration

12 Pin Connect Block

13 General-Purpose Input/Output (GPIO) Ports

14 Universal Asynchronous Receiver/Transmitter 0 (UART0)

15 Universal Asynchronous Receiver/Transmitter 1 (UART1)

I 2 C Interfaces I

C0 and I 2 C1

17 SPI Interface SPI0

18 SPI/SSP Interface SPI1

19 Analog-To-Digital Converter (ADC)

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Summary of Contents for NXP Semiconductors MPT612