Lsi Pin Description（Lsi 端子機能表 - Yamaha MR816CSX Service Manual

MR816CSX/MR816X
LSI PIN DESCRIPTION（LSI 端子機能表）
1394AV-L (X6893A00) DICE II ..................................................................................................... 16
AK4358VQ (X4289A00) DAC (Digital to Analog Converter) ................................................................20
AK5385BVF-E2 (X5364B00) ADC (Analog to Digital Converter) ........................................................19
EP1C3T100C8N (X5691A00) FPGA....................................................................................................14
MB87S1280 (X6363A00) SSP1 (MAIN/SUB) ......................................................................................18
MN101C027YB (XS71120R) CPU .......................................................................................................15
S1L50553F21Y000 (X4195A0R) MCI (Gate Array) .............................................................................19
TSB41AB2PAP (XZ665A00) PHY .......................................................................................................15
YAC523-VZ (X4325A00) EVR2 (Electric Variable Resistance 2) .........................................................20
EP1C3T100C8N (X5691A00) FPGA
PIN
NAME I/O
NO.
1 IO I/O PAD[4]
2 IO I/O PAD[3]
AVC_SCLK
3 IO I/O
AVC_DATAI
4 IO I/O
AVC_CS
5 IO I/O
6 nCSO O Chip select output that enables/disables a
serial configuration device.
7 DATA0 I Dedicated configuration data input pin
8 nCONFIG I Dedicated configuration control input
9 VCCA_PLL1 - Analog power for PLL1
10 CLK0 I Dedicated global clock input
11 GNDA_PLL1 - Analog ground for PLL1
Output that drives low when device configu-
12 nCEO O
ration is complete.
Active-low chip enable
13 nCE I
14 MSEL0 I Dedicated mode select control pins that set
the configuration mode for the device.
15 MSEL1 I
16 DCLK I/O Clock input (PS mode) or output (AS mode)
17 ASDO O Active serial data output from the Cyclone device
18 VCCIO1 - I/O supply voltage pin for bank 1
19 GND - Ground
P48V[8]
20 IO I/O
P48V[7]
21 IO I/O
P48V[6]
22 IO I/O
P48V[5]
23 IO I/O
24 IO I/O P48V[4]
25 IO I/O P48V[3]
26 IO I/O DA4358_CS
27 IO I/O DA4382_CS
28 IO I/O DA_CDTI
29 IO I/O DA_CCLK
Ground
30 GND -
I/O supply voltage pin for bank 4
31 VCCIO4 I/O
Ground
32 GND -
Internal logic array voltage supply pin
33 VCCINT -
34 IO I/O CLK18M
35 IO I/O P48V[1]
36 IO I/O PAD[1]
37 IO I/O P48V[2]
38 IO I/O PAD[2]
39 IO I/O Analog_MUTE
DSP_MUTE/DAC1_MUTE/
40 IO I/O
DAC2_MUTE
MUTE_REQ
41 IO I/O
42 IO I/O MUTE_OFF
43 GND - Ground
44 VCCINT - Internal logic array voltage supply pin
45 GND - Ground
46 VCCIO4 I/O I/O supply voltage pin for bank 4
47 IO I/O EN[1]
48 IO I/O EN[2]
EN[3]
49 IO I/O
14
FUNCTION
Data I/Os
Data I/Os
Data I/Os
Data I/Os
PIN
NAME I/O
NO.
50 IO I/O EN[4]
51 IO I/O MMD[7]
52 IO I/O MMD[6]
53 IO I/O MMD[5]
54 IO I/O MMD[4]
55 IO I/O MMD[3]
56 IO I/O MMD[2]
57 IO I/O MMD[1]
58 GND - Ground
59 VCCIO3 I/O I/O supply voltage pin for bank 3
60 CONF_DONE -
Dedicated configuration status pin
61 nSTATUS -
62 TCK I
Dedicated JTAG input pin
63 TMS I
64 TDO O Dedicated JTAG output pin
65 IO I/O MMD[0]
66 CLK2 I Dedicated global clock input
67 TDI I Dedicated JTAG input pin
68 IO I/O CD60RD
69 IO I/O CS61WR
70 IO I/O CS62WR
71 IO I/O CS63WR
72 IO I/O MMA[1]
73 IO I/O MIRQ
74 IO I/O MCI_SIRQ
75 IO I/O DICE_IRQO
76 IO I/O DA_MUTE
77 IO I/O DICE_MUTE
78 IO I/O AES_MUTE/WCK_MUTE
79 IO I/O FW_MUTE
80 VCCIO2 I/O I/O supply voltage pin for bank 2
81 GND - Ground
82 VCCINT - Internal logic array voltage supply pin
83 GND - Ground
84 IO I/O FS_CLK
85 IO I/O TL1
86 IO I/O DODATA[2]
87 IO I/O DODATA[1]
88 IO I/O DIDATA[2]
89 IO I/O DIDATA[1]
90 IO I/O DSAI_DO
91 IO I/O DSAI_DI
92 IO I/O DSAI_Fs
93 VCCINT - Internal logic array voltage supply pin
94 GND - Ground
95 VCCIO2 I/O I/O supply voltage pin for bank 2
96 GND - Ground
97 IO I/O PAD[8]
98 IO I/O PAD[7]
99 IO I/O PAD[6]
100 IO I/O PAD[5]
17
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DM: IC123
FUNCTION
Data I/Os
Data I/Os
Data I/Os
Data I/Os