Yamaha MR816CSX Service Manual page 17

PIN OUTER
NAME I/O
NO. NO.
137 L1 A9 O
138 L2 A10 O
139 L3 A11 O
140 L4 A12 O
141 L9 VSS3OP –
142 L10 VSS3OP –
143 L11 VSS3OP –
144 L12 VSS3OP –
145 L17 VDD3OP –
146 L18 HPX3 I/O
147 L19 PLL_1V8 (HPLL1) –
148 L20 HPX2 O
149 M1 A13 O
150 M2 A14 O
151 M3 A15 O
152 M4 A16 O
153 M9 VSS3OP –
154 M10 VSS3OP –
155 M11 VSS3OP –
156 M12 VSS3OP –
157 M17 FILTER_HPLL2 A
158 M18 PLL_GND (HPLL1) –
159 M19 PLL_BULK (HPLL1) –
160 M20 FILTER_HPLL1 A
161 N1 A17 O
162 N2 A18 O
163 N3 A19 O
164 N4 VSS3OP –
165 N17 VSS3OP –
166 N18 PLL_GND (HPLL2) –
167 N19 PLL_BULK (HPLL2) –
168 N20 PLL_1V8 (HPLL2) –
169 P1 A20/CS7/EN1_A I/O
170 P2 A21/CS6/EN1_B I/O
171 P3 I/O
A23/CS4/EN2_B/GPO6
172 P4 CLKO O
173 P17 VSS3I –
174 P18 –
PLL_BULK (CLK_CBL)
175 P19 –
PLL_1V8 (CLK_DBL)
176 P20 FILTER_CLK_DBL A
177 R1 A22/CS5/EN2_A I/O
178 R2 VSS3I –
179 R3 GPIO1/CLKE I/O
180 R4 VDD3OP –
181 R17 VDD3OP –
182 R18 XTAL1 I
183 R19 VDD1IH –
184 R20 –
PLL_GND (CLK_DBL)
185 T1 VDD1IH –
186 T2 RAS O
187 T3 SDRAM_WE O
188 T4 SDRAM_DQM1 O
189 T17 DSAI_TX0 O
190 T18 DSAI_TX3 O
191 T19 VDD3OP –
192 T20 XTAL2 O
193 U1 CAS O
194 U2 CS1 O
195 U3 SDRAM_BNK0 O
196 U4 VSS3OP –
197 U5 PHD5 I/O
198 U6 VDD3OP –
199 U7 PHLP O
200 U8 VSS3OP –
201 U9 I/O
VD5/TDF_IFS0/U1_DSR/HFS1
202 U10 VDD3OP –
203 U11 I/O
GPIO15/WCKO/TDF_OEM/U0_OUT2
204 U12 FILTER_TDIF A
FUNCTION
Address bus
I/O ground
I/O 3.3V
GPIO
PLL 1.8V
GPIO(Z)
Address bus
I/O ground
JETPLL filter component connection
PLL ground
PLL bulk bias
JETPLL filter component connection
Address bus
I/O ground
PLL ground
PLL bulk bias
PLL 1.8V
Address bus / Chip select / Rotary encoder input
Address bus / Chip select / Rotary encoder input / General purpose
SDRAM interface AHB Bus clock
Core ground
PLL bulk bias
PLL 1.8V
Clock Doubler VCO filter component connection
Address bus / Chip select / Rotary encoder input
Core ground
General purpose I/O / SDRAM interface Clock enable
I/O 3.3V
XTAL for clock doubler/power manager/LLC
Core 1.8V
PLL ground
Core 1.8V
SDRAM interface Row address strobe
SDRAM interface Write enable
SDRAM interface Upper byte mask
DSAI Transmitter 0 data line
DSAI Transmitter 3 data line
I/O 3.3V
XTAL for clock doubler/power manager/LLC
SDRAM interface Column address strobe
Chip select
SDRAM interface Bank addsess
I/O ground
PHY tristable data line bit 5
I/O 3.3V
Link power status. Pulsing if isolation barrier present.
I/O ground
Video interface - Data byte bit 5 / TDIF sample rate 0 input / Data set ready UART status input / 512fs base rate clock
I/O 3.3V
General purpose I/O / Word clock out / TDIF emphasis output / UART control programmable output 2 output
TDIF Receiver VCO filter component connection
PIN OUTER
NAME I/O
NO. NO.
205 U13 VSS3OP –
206 U14 AES_RX2 I
207 U15 VDD3OP –
208 U16 DSAI_RX1 I
209 U17 VSS3OP –
210 U18 DSAI_SYNCD I/O
211 U19 DSAI_CKD I/O
212 U20 DSAI_TX2 O
213 V1 SDRAM_DQM0 O
214 V2 SDRAM_BNK1 O
215 V3 I/O
EN3_B/GPIO3/SDRAM_BNK3
216 V4 PHD4 I/O
217 V5 PHCT0 I/O
218 V6 PHLR O
219 V7 VDD1IH –
220 V8 I/O
VD2/TDF_I2/U0_DCD
221 V9 I/O
VD6/TDF_IFS1/U1_DCD/HFS2
222 V10 I/O
VCLK/TDF_O2/U1_OUT1
223 V11 I/O
GPIO14/WCKI/TDF_OFS1/U0_OUT1
224 V12 –
PLL_1V8 (AES,ADAT,TDIF)
225 V13 –
PLL_GND (AES,ADAT,TDIF)
226 V14 EXT_512BR I/O
227 V15 AES_RX3 I
228 V16 AES_TX2 O
229 V17 DSAI_RX2 I
230 V18 DSAI_SYNCA I/O
231 V19 DSAI_SYNCC I/O
232 V20 DSAI_TX1 O
233 W1 I/O
EN3_A /GPIO2/SDRAM_BNK2
234 W2 SCLK I
235 W3 PHD1 I/O
236 W4 PHD3 I/O
237 W5 PHCT1 I/O
238 W6 PHLO I
239 W7 I/O
VD0/TDF_I0/U0_CTS
240 W8 I/O
VD3/TDF_I3/U0_RI
241 W9 I/O
VD7/TDF_IEM/U1_RI
242 W10 I/O
VRDY/TDF_O1/U1_RTS
243 W11 I/O
GPIO13/BLKS/TDF_OFS0/U0_RTS
244 W12 VSS3I –
245 W13 FILTER_AES A
246 W14 OPTI I
247 W15 AES_RX0 I
248 W16 AES_TX0 O
249 W17 AES_TX3 O
250 W18 DSAI_RX3 I
251 W19 DSAI_CKB I/O
252 W20 DSAI_CKC I/O
253 Y1 PHD0 I/O
254 Y2 PHD2 I/O
255 Y3 PHD6 I/O
256 Y4 PHD7 I/O
257 Y5 PHDI I
258 Y6 VSS3I –
259 Y7 I/O
VD1/TDF_I1/U0_DSR
260 Y8 I/O
VD4/TDF_ILR/U1_CTS
261 Y9 I/O
VFSYNC/TDF_O0/U1_DTS
262 Y10 I/O
VEND_DB/TDF_O3/U1_OUT2
263 Y11 I/O
VVALID/TDF_OLR/U0_DTS
264 Y12 VDD1IH –
265 Y13 FILTER_ADAT A
266 Y14 OPTP O
267 Y15 EXT_FBR I/O
268 Y16 AES_RX1 1
269 Y17 AES_TX1 O
270 Y18 DSAI_RX0 I
271 Y19 DSAI_CKA I/O
272 Y20 DSAI_SYNCB I/O
MR816CSX/MR816X
FUNCTION
I/O ground
AES3 Receiver ch4/5
I/O 3.3V
DSAI Receiver 1 data line
I/O ground
DSAI Sync D
DSAI Clock D
DSAI Transmitter 2 data line
SDRAM interface Lower byte mask
SDRAM interface Bank addsess
Rotary encoder input / General purpose I/O / SDRAM interface Bank addsess
PHY tristable data line bit 4
PHY tristable control line bit 0
Serial request output from S-LINK(Z)
Core 1.8V
Video interface - Data byte bit 2 / TDIF audio data input 3 / Data carrier detect UART status input
Vi d eo i n terface - Data byte bi t 6 / TDIF sampl e rate 1 i n put / Data carri e r detect UART status i n put / 512fs base rate cl o ck
Video interface - Video Clock / TDIF audio data output 3 / UART control programmable output 1 output
General purpose I/O / Word clock in / TDIF sample rate 1 output / UART control programmable output 1 output
PLL 1.8V
PLL ground
External 512 x base rate clock
AES3 Receiver ch.6/7
AES3 Transmitter ch.4/5
DSAI Receiver 2 data line
DSAI Sync A
DSAI Sync C
DSAI Transmitter 1 data line
Rotary encoder input / General purpose I/O / SDRAM interface Bank addsess
49.152MHz PHY Clock input
PHY tristable data line bit 1
PHY tristable data line bit 3
PHY tristable control line bit 1
Link on indication from PHY. Pulsing when asserted.
Video interface - Data byte bit 0 / TDIF audio data input 1 / Clear to send UART status input
Video interface - Data byte bit 3 / TDIF audio data input 4 / Ring indicator UART status input
Video interface - Data byte bit 7 / TDIF emphasis input / Ring indicator UART status input
Video interface - Video ready signal / TDIF audio data output 2 / UART control request to send output
General purpose I/O / Bl o ck sync i n put/output si g nal / TDIF sampl e rate 0 output / UART control request to send output
Core ground
AES Receiver filter component connection
Optical audio in
AES3 Receiver ch.0/1
AES3 Transmitter ch.0/1
AES3 Transmitter ch.6/7
DSAI Receiver 3 data line
DSAI Clock B
DSAI Clock C
PHY tristable data line bit 0
PHY tristable data line bit 2
PHY tristable data line bit 6
PHY tristable data line bit 7
A high indicates isolation barrier is not present.
Core ground
Video interface - Data byte bit 1 / TDIF audio data input 2 / Data set ready UART status input
Video interface - Data byte bit 4 / TDIF left right clock input / Clear to send UART status input
Video interface - Video sync signal / TDIF audio data output 1 / UART control data terminalready output
Video interface - End of Data block / TDIF audio data output 4 / UART control programmable output 1 output
Video interface - Video data valid / TDIF left right clock output / UART control data terminal ready output
Core 1.8V
ADAT Receiver filter component connection
Optical audio out
External 1fs base rate clock
AES3 Receiver ch.2/3
AES3 Transmitter ch.2/3
DSAI Receiver 0 data line
DSAI Clock A
DSAI Sync B
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