Yamaha MR816CSX Service Manual page 48

MR816CSX/MR816X
<2-2-6> Jitter measurement (WORD CLOCK
INTERNAL)
Measure the [S/PDIF OUT] (COAXIAL) terminal.
Set WORD CLOCK to INTERNAL.
Check that the jitter measurement value is as
follows:
WORD CLOCK
44.1 kHz
48 kHz
88.1 kHz
96 kHz
<2-2-7> Jitter measurement (WORD CLOCK EXT)
Measure the [S/PDIF OUT] (COAXIAL) terminal.
Set up the WORD CLOCK and frequency of input
sources as follows:
Check of WORD CLOCK IN: WCLK
Check of ADAT :
Check of S/PDIF :
Check that the jitter measurement value is as
follows:
WORD CLOCK
44.1 kHz
48 kHz
88.1 kHz
96 kHz
* Be sure to execute Factory set after fi nishing digital
characteristic inspection. (Refer to " FACTORY SET "
on P. 40)
5-2. No. 1 MEMORY test
5-2-1. Outline
Check the ROM/RAM device around the SSP1 on the
DM circuit board and connection of signal cables between
devices.
5-2-2. Main devices to be tested
• FLASH ROM
• SDRAM(SSP1 SUB)
• SRAM
• EEPROM
5-2-3. Test method
Turn the [ASSIGN 1] encoder to turn on the LED
corresponding to the MEMORY test and then press the
[ASSIGN 1] encoder to execute the test.
Test of ROM/RAMs will be executed automatically.
The LED for the [ASSIGN 2] encoder corresponding to
the MEMORY test lights up if the test result is OK or
doesn't light if the result is NG.
48
Tolerance
5 nsec or
below
ADAT
S/PDIF
Tolerance
5 nsec or
below
ASSIGN 1
1. MEMORY
(Test item selection)
(Fig. 11)
5-2-4. Test contents
The result of the test is OK if test result of all the ROM/
RAMs around the SSP1 is OK. The result of the test is
OK if test result of any one of the ROM/RAMs around the
SSP1 is NG.
• FLASH ROM
CFI Query information of FLASH ROM is read from the
SSP1.
If correct information is obtained, the signal cable between
the SSP1 and Flash ROM should be connected properly
and the test result is OK.
• SRAM
Checking of data bus and address bus connection between
the SSP1 and SRAM is conducted.
• SDRAM (SSP1 SUB)
Checking of data bus and address bus connection between
the SSP1 SUB and SDRAM is conducted. The test uses
the signal cable between the SSP1 MAIN and SSP1 SUB
and the test result also shows if the connection of the
signal cable between the SSP1 MAIN and SSP1 SUB is
normal.
• EEPROM
Issue Write Disable command from the SSP1 to EEPROM
and then issue Read Status Register command and check
that WEL bit is not on. Next, issue Write Enable command
and then issue Read Status Register command and check
that WEL bit is on. If both the WEL bits are read properly,
the signal cable between the SSP1 and EEPROM should
be connected properly and the test result is OK.
5-3. No.2 LED test
5-3-1. Outline
Executes device check of LED on the PN circuit board
and panel micro computer, and connection check of signal
cables between LED, panel micro computer and SSP1.
ASSIGN 2
1. MEMORY
(Test result)