Eaton EDR-5000 Installation, Operation And Maintenance Manual page 645

Name
Logic.LE14.Gate Out
Logic.LE14.Timer Out
Logic.LE14.Out
Logic.LE14.Out inverted
Logic.LE15.Gate Out
Logic.LE15.Timer Out
Logic.LE15.Out
Logic.LE15.Out inverted
Logic.LE16.Gate Out
Logic.LE16.Timer Out
Logic.LE16.Out
Logic.LE16.Out inverted
Logic.LE17.Gate Out
Logic.LE17.Timer Out
Logic.LE17.Out
Logic.LE17.Out inverted
Logic.LE18.Gate Out
Logic.LE18.Timer Out
Logic.LE18.Out
Logic.LE18.Out inverted
Logic.LE19.Gate Out
Logic.LE19.Timer Out
Logic.LE19.Out
Logic.LE19.Out inverted
Logic.LE20.Gate Out
Logic.LE20.Timer Out
Logic.LE20.Out
Logic.LE20.Out inverted
Logic.LE21.Gate Out
Logic.LE21.Timer Out
Logic.LE21.Out
Logic.LE21.Out inverted
Logic.LE22.Gate Out
Logic.LE22.Timer Out
Logic.LE22.Out
Logic.LE22.Out inverted
Logic.LE23.Gate Out
Description
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
Signal: Output of the logic gate
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EDR-5000 IM02602007E
645