Eaton EDR-5000 Installation, Operation And Maintenance Manual page 994

Name
Logic.LE48.Gate Out
Logic.LE48.Timer Out
Logic.LE48.Out
Logic.LE48.Out inverted
Logic.LE48.Gate In1-I
Logic.LE48.Gate In2-I
Logic.LE48.Gate In3-I
Logic.LE48.Gate In4-I
Logic.LE48.Reset Latch-I
Logic.LE49.Gate Out
Logic.LE49.Timer Out
Logic.LE49.Out
Logic.LE49.Out inverted
Logic.LE49.Gate In1-I
Logic.LE49.Gate In2-I
Logic.LE49.Gate In3-I
Logic.LE49.Gate In4-I
Logic.LE49.Reset Latch-I
Logic.LE50.Gate Out
Logic.LE50.Timer Out
Logic.LE50.Out
Logic.LE50.Out inverted
Logic.LE50.Gate In1-I
Logic.LE50.Gate In2-I
Logic.LE50.Gate In3-I
Logic.LE50.Gate In4-I
Logic.LE50.Reset Latch-I
Logic.LE51.Gate Out
Logic.LE51.Timer Out
Logic.LE51.Out
Logic.LE51.Out inverted
Logic.LE51.Gate In1-I
Logic.LE51.Gate In2-I
Logic.LE51.Gate In3-I
Logic.LE51.Gate In4-I
Logic.LE51.Reset Latch-I
Logic.LE52.Gate Out
Description
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
Signal: Timer Output
Signal: Latched Output (Q)
Signal: Negated Latched Output (Q NOT)
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Assignment of the Input Signal
State of the module input: Reset Signal for the Latching
Signal: Output of the logic gate
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EDR-5000 IM02602007E
994