Functional Description; Overview - Profichip VPC3+C User Manual

2.1

Overview

The VPC3+C makes a cost optimized design of intelligent PROFIBUS DP-
Slave applications possible.
The processor interface supports the following processor series:
The VPC3+C handles the physical layer 1 and the data link layer 2 of the
ISO/OSI-reference-model excluding the analog RS485 drivers.
The integrated 4K Byte Dual-Port-RAM serves as an interface between
the VPC3+C and the software/application. In case of using 2K Byte the
entire memory is divided into 256 segments, with 8 bytes each. Otherwise
in the 4K Byte mode the segment base addresses starts at multiple of 16.
Addressing by the user is done directly, however, the internal Micro
Sequencer (MS) addresses the RAM by means of the so-called base-
pointer. The base-pointer can be positioned at the beginning of a segment
in the memory. Therefore, all buffers must be located at the beginning of a
segment.
If the VPC3+C carries out a DP communication it automatically sets up all
DP-SAPs. The various telegram information are made available to the user
in separate data buffers (for example, parameter and configuration data).
Three buffers are provided for data communication (three for output data
and three for input data). As one buffer is always available for communica-
tion no resource problems can occur. For optimal diagnosis support, the
VPC3+C offers two Diagnosis-Buffers. The user enters the updated
diagnosis data into these buffers. One Diagnosis-Buffer is always assigned
to the VPC3+C.
The Bus Interface Unit is a parameterizable synchronous/asynchronous 8-
bit interface for various Intel and Motorola microcontrollers/processors. The
user can directly access the internal 2K/4K Byte RAM or the parameter
latches and control registers via the 11/12-bit address bus.
Procedure-specific parameters (Station_Address, control bits, etc.) must be
transferred to the Parameter Registers and to the Mode Registers after
power-on.
The MAC status can be observed at any time in the Status Register.
Various events (e.g. various indications, error events, etc.) are entered in
the Interrupt Controller. These events can be individually enabled via a
mask register. Acknowledgement takes place by means of the acknowl-
edge register. The VPC3+C has a common interrupt output.
VPC3+C User Manual
Copyright © profichip GmbH 2004-2006

Functional Description

Intel: 80C31, 80X86
Siemens: 80C166/165/167
Motorola: HC11-, HC16-, and HC916 types
Revision 1.03
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2 Functional Description
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