Hardware Interface; Universal Processor Bus Interface; Overview; Bus Interface Unit - Profichip VPC3+C User Manual

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Table of Contents

8.1

Universal Processor Bus Interface

8.1.1

Overview

The VPC3+C has a parallel 8-bit interface with an 11-bit address bus. The

VPC3+C supports all 8-bit processors and microcontrollers based on the

80C51/52 (80C32) from Intel, the Motorola HC11 family, as well as 8- /16-

bit processors or microcontrollers from the Siemens 80C166 family, X86

from Intel and the HC16 and HC916 family from Motorola. Because the

data formats from Intel and Motorola are not compatible, VPC3+C

automatically carries out 'byte swapping' for accesses to the following 16-

bit registers (Interrupt Register, Status Register and Mode Register 0) and

the 16-bit RAM cell (R_User_WD_Value). This makes it possible for a

Motorola processor to read the 16-bit value correctly. Reading or writing

takes place, as usual, through two accesses (8-bit data bus).

The Bus Interface Unit (BIU) and the Dual Port RAM Controller (DPC) that

controls accesses to the internal RAM belong to the processor interface of

the VPC3+C.

The VPC3+C is supplied with a clock pulse rate of 48MHz. In addition, a

clock divider is integrated. The clock pulse is divided by 2 (Pin: DIVIDER =

'1') or 4 (Pin: DIVIDER = '0') and applied to the pin CLKOUT 2/4. This

allows the connection of a slower controller without additional expenditures

in a low-cost application.

8.1.2

Bus Interface Unit

The Bus Interface Unit (BIU) is the interface to the connected

processor/microcontroller. This is a synchronous or asynchronous 8-bit

interface with an 11-bit (12-bit in 4K Byte mode) address bus. The interface

is configurable via 2 pins (XINT/MOT, MODE). The connected processor

family (bus control signals such as XWR, XRD, or R_W and the data

format) is specified with the XINT/MOT pin. Synchronous or asynchronous

bus timing is specified with the MODE pin.

XINT/MOT

Figure 8-1: Configuration of the Processor Interface

Examples of various Intel system configurations are given in subsequent

sections. The internal address latch and the integrated decoder must be

VPC3+C User Manual