VPC3+C in existing applications without any restrictions or SW- modifications. However, downgrading from VPC3+C to VPC3+ is only possible, if the additional features of VPC3+C (4K Byte RAM, DP-V1- or DP-V2-functionality, 3.3V supply) are not used. As there are also simple devices in the automation engineering area, such...
80C166/165/167 Motorola: HC11-, HC16-, and HC916 types The VPC3+C handles the physical layer 1 and the data link layer 2 of the ISO/OSI-reference-model excluding the analog RS485 drivers. The integrated 4K Byte Dual-Port-RAM serves as an interface between the VPC3+C and the software/application. In case of using 2K Byte the entire memory is divided into 256 segments, with 8 bytes each.
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Station_Address, etc.) and the data buffers. In the UART, the parallel data flow is converted into the serial data flow and vice-versa. The VPC3+C is capable of automatically identifying the baud rates (9.6 Kbit/s - 12 Mbit/s). The Idle Timer directly controls the bus times on the serial bus line.
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Beginning with Step B of the VPC3+ the communication RAM has been extended to 4K Byte, whereas Step A only has 2K Byte. To access the entire 4K Byte RAM in VPC3+C an additional address signal AB11 is required. Which pin is assigned to A11 depends on the Processor Interface Mode used (see Figure 3-2).
Control Parameters (Latches/Registers) These cells can be either read-only or write-only. In the Motorola Mode the VPC3+C carries out ‘address swapping’ for an access to the address locations 00H - 07H (word registers). That is, the VPC3+C internally generates an even address from an odd address and vice-versa.
These parameters can be written and read. Address Intel Mot. Name Bit No. Significance R_TS_Adr Setup Station_Address of the VPC3+C Pointer to a RAM address which is preset SAP_List_Ptr with FFh or to SAP-List R_User_WD_Value 7..0 In DP_Mode an internal 16-bit watchdog timer monitors the user.
**) When a large number of parameters have to be transmitted from the DP-Master to the DP-Slave, the Aux-Buffer 1/2 must have the same length as the Parameter-Buffer. Sometimes this could reach the limit of the available memory in the VPC3+C. When Spec_Prm_Buf_Mode = 1 the parameterization data are processed directly in this special buffer and the Aux-Buffers can be held compact.
1 = PrmCmd is supported bit 13 Spec_Clear_Mode: Special Clear Mode (Fail Safe Mode) 0 = No special clear mode. 1 = Special clear mode. VPC3+C will accept data telegrams with data unit = 0 bit 12 Spec_Prm_Buf_Mode: Special-Parameter-Buffer Mode 0 = No Special-Parameter-Buffer.
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After this action, VPC3+ sets User_LEAVE-MASTER to ’0’ again. bit 2 Go_Offline: Going into the Offline state 1 = After the current request ends, VPC3+C goes to the Offline state and sets Go_Offline to ’0’ again. bit 1 EOI: End-of-Interrupt 1 = VPC3+C disables the interrupt output and sets EOI to ’0‘...
ASIC Interface 5 Status Register The Status Register shows the current VPC3+C status and can be read only. Bit Position Address Designation Status-Reg WD_State DP_State (Intel) 7..0 See below for coding Bit Position Address Designation Status-Reg (Intel) 15..8 VPC3+ Release...
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ASIC Interface 5 Interrupt-Request-Register, Low-Byte, Address 00H (Intel): bit 7 DXB_Out: VPC3+C has received a DXB telegram and made the new output data available in the ‘N’ buffer. bit 6 New_Ext_Prm_Data: The VPC3+C has received a Set_Ext_Prm telegram and made the data available in the Parameter-Buffer.
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5 ASIC Interface Interrupt Request Register 0, High-Byte, Address 01H (Intel): bit 15 FDL_Ind: The VPC3+C has received an acyclic service request and made the data available in an Indication-Buffer. bit 14 Poll_End_Ind: The VPC3+C have send the response to an acyclic service.
User_Prm_Data_Okay etc.). Watchdog Timer The VPC3+C is able to identify the baud rate automatically. The state ma- chine is in the BAUD_SEARCH state after each RESET and also after the Watchdog (WD) Timer has expired in the BAUD_CONTROL state.
5 ASIC Interface 5.4.1 Automatic Baud Rate Identification The VPC3+C starts searching for the transmission rate using the highest baud rate. If no SD1 telegram, SD2 telegram, or SD3 telegram was received completely and without errors during the monitoring time, the search continues using the next lower baud rate.
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ASIC Interface 5 If the monitoring time expires, the VPC3+C goes to BAUD_CONTROL state again and generates the WD_DP_CONTROL_Timeout interrupt. In addition, the DP State Machine is reset, that is, it generates the reset states of the buffer management. This operation mode is recommended for the most applications.
PROFIBUS DP Interface PROFIBUS DP Interface DP Buffer Structure The DP_Mode is enabled in the VPC3+C with ‘DP_Mode = 1’ (see Mode Register 0). In this mode, the following SAPs are permanently reserved: Default SAP: Write and Read data (Data_Exchange)
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Parameter- Buffer Figure 6-1: DP_SAP Buffer Structure The VPC3+C first stores the parameter telegrams (Set_Slave_Add and Set_(Ext_)Prm) and the configuration telegram (Chk_Cfg) in Aux-Buffer 1 or Aux-Buffer 2. If the telegrams are error-free, data is exchanged with the corresponding target buffer (Set_Slave_Add-Buffer, Parameter-Buffer and Config-Buffer).
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Aux-Buffer 2 available (R_Aux_Buf_Sel: Set_Prm = 1) for this telegram. The other telegrams are then read via Aux-Buffer 1 (R_Aux_Buf_Sel: Set_Slave_Adr = 0, Chk_Cfg = 0). If the buffers are too small, the VPC3+C responds with “no resources” (RR)! Bit Position...
R_TS_Adr und R_Real_No_Add_Change RAM registers. If SAP55 is enabled and the Set_Slave_Add telegram is received correctly, the VPC3+C enters the pure data in the Aux-Buffer 1/2, exchanges the Aux-Buffer 1/2 for the Set_Slave_Add-Buffer, stores the entered data length in R_Len_SSA_Data, generates the New_SSA_Data interrupt and internally stores the New_Slave_Add as Station_Address and the No_Add_Chg as Real_No_Add_Chg.
User_Prm_Data), or the first eight data bytes (with User_Prm_Data). The first seven bytes are specified according to the standard. The eighth byte is used for VPC3+C specific characteristics. The additional bytes are available to the application. If a PROFIBUS DP extension shall be used, the bytes 7-9 are called DPV1_Status and must be coded as described in section 7, “PROFIBUS DP Extensions”.
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In the case of a positive validation of more than seven data bytes, the VPC3+C carries out the following reaction: The VPC3+C exchanges Aux-Buffer 1/2 (all data bytes are entered here) for the Parameter-Buffer, stores the input data length in R_Len_Prm_Data and triggers the New_Prm_Data interrupt.
Cfg_Conflict signal during the positive or negative acknowledgement of the first Chk_Cfg telegram. Then the user must repeat the validation, because the VPC3+C have made a new Config-Buffer available. The User_Cfg_Data_Okay_Cmd and User_Cfg_Data_Not_Okay_Cmd acknowledgements are read accesses to defined memory cells with the relevant Not_Allowed, User_Cfg_Finished, or Cfg_Conflict signals.
Two buffers are available for diagnosis. These two buffers can have different lengths. One Diagnosis-Buffer, which is sent on a diagnosis request, is always assigned to the VPC3+C. The user can pre-process new diagnosis data in the other buffer parallel. If the new diagnosis data are to...
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Figure 6-9: Diagnosis Buffer Assignment The New_Diag_Cmd is also a read access to a defined control parameter indicating which Diagnosis-Buffer belongs to the user after the exchange or whether both buffers ar e currently assigned to the VPC3+C (No_Buffer, iag_Buf1, Diag_Buf2). Bit Position Address...
For power-on, LEAVE-MASTER and the Global_Control telegram with ‘Clear_Data = 1’, the VPC3+C deletes the ‘D’ buffer and then shifts it to ‘N'. This also takes place during power-up (entering the WAIT-PRM state). If the user fetches this buffer, he receives U_Buffer_Cleared during the Revision 1.03...
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(cleared) data can be sent for a RD_Output telegram before the first data cycle. Reading Inputs The VPC3+C sends the input data from the ‘D’ buffer. Prior to sending, the VPC3+C fetches the Din-Buffer from ‘N’ to ‘D'. If no new buffer is present in ‘N', there is no change. user makes...
The interrupt behavior regarding to the reception of a Global_Control telegram can be configured via bit 8 of Mode Register 2. The VPC3+C either generates the New_GC_Control interrupt after each receipt of a Global_Control telegram (default) or just in case if the Global_Control differs from the previous one.
6.2.8 RD_Output (SAP 57) The VPC3+C fetches the output data from the Dout_Buffer in ‘U’. The user must preset the output data with ‘0’ during start-up so that no invalid data can be sent here. If there is a buffer change from ‘N’ to ‘U’ (through the Next_Dout_Buffer_Cmd) between the first call-up and the repetition, the new output data is sent during the repetition.
Config-Buffer, sets ‘En_Change_Cfg_buffer = 1’ (see Mode Register 1) and the VPC3+C then exchanges the Config-Buffer for the Read_Config-Buffer. If there is a change in the configuration data during operation (for example, for a modular DP systems), the user must return with Go_Offline command (see Mode Register 1) to WAIT-PRM.
If the DP-Slave requires Fail_Safe but the DP-Master doesn’t the Prm_Fault bit is set. If the VPC3+C should be used for DXB, IsoM or redundancy mode, the parameterization data must be packed in a Structured_Prm_Data block to distinguish between the User_Prm_Data. The bit Prm_Structure indicates this.
PROFIBUS DP-V1 7.2.1 Acyclic Communication Relationships The VPC3+C supports acyclic communication as described in the DP-V1 specification. Therefore a memory area is required which contains all SAPs needed for the communication. The user must do the initialization of this area (SAP-List) in Offline state. Each entry in the SAP-List consists of 7 bytes.
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SAP_Number: 0 – 51 Byte 1 Request_SA: The source address of a request is compared with this value. At differences, the VPC3+C response with “no service activated” (RS). The default value for this entry is 7FH. Byte 2 Request_SSAP: The source SAP of a request is compared with this value. At differences, the VPC3+C response with “no service activated”...
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(RS) or if no free buffer is available with “no resource” (RR). After finishing the processing of the incoming telegram, the INUSE bit is reset and the bits USER and IND are set by VPC3+C. Now the FDL_Ind interrupt is generated. Polling telegrams do not produce interrupts. The RESP bit indicates response data, provided by the user in the Response- Buffer.
Poll_End_Ind interrupt clear Poll_End_Ind interrupt search for SAP with Response_Sent = 1 clear Response_Sent Figure 7-6: FDL-Interface of VPC3+C (e.g. same Buffer for Indication and Response) 7.2.2 Diagnosis Model The format of the device related diagnosis data depends on the GSD keyword DPV1_Slave in the GSD.
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The VPC3+C processes DXBout-Buffers like the Dout-Buffers. The only difference is that the DXBout-Buffers are not cleared by the VPC3+C. The VPC3+C writes the received and filtered broadcast data in the 'D' buffer. The buffer contains also the Publisher_Address and the Sample_Length.
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In state DATA-EXCH the links are monitored in intervals defined by the parameterized watchdog time. After the monitoring time runs out, the VPC3+C evaluates the Link_Status of each Publisher and updates the bit Link_Status. The timer restarts again automatically. Link_...
The IsoM synchronizes DP-Master, DP-Slave and DP-Cycle. The isochron cycle time starts with the transmission of the SYNCH telegram by the IsoM master. If the VPC3+C supports the IsoM, a synchronization signal at Pin 13 (XDATAEXCH/SYNC) is generated by each reception of a SYNCH telegram.
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Isochron Mode To enable the Isochron Mode in the VPC3+C, bit SYNC_Ena in Mode Register 2 must be set. Additionally the Spec_Clear_Mode in Mode Register 0 must be set. The polarity of the SYNC signal can be adjusted with the SYNC_Pol bit.
RAM belong to the processor interface of the VPC3+C. The VPC3+C is supplied with a clock pulse rate of 48MHz. In addition, a clock divider is integrated. The clock pulse is divided by 2 (Pin: DIVIDER = '1') or 4 (Pin: DIVIDER = '0') and applied to the pin CLKOUT 2/4.
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8 Hardware Interface used in the synchronous Intel mode. One figure shows the minimum con- figuration of a system with the VPC3+C, where the chip is connected to an EPROM version of the controller. Only a clock generator is necessary as an additional device in this configuration.
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The lower address bits AB7..0 are stored with the ALE signal in an in- ternal address latch. The internal CS decoder is activated. VPC3+C generates its own CS signal from the address lines AB10..3. The VPC3+C selects the relevant address window from the AB2..0 signals.
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This means additional hardware and a fixed assignment. If the CPU is clocked by the VPC3+C, the output clock pulse (CLKOUT 2/4) must be 4 times larger than the E_Clock. That is, a clock pulse sig- nal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse (E_Clock).
Figure 8-6: 80C32 Application in 2K Byte mode The internal chipselect is a ctivated when the address inputs AB[10..3] of the VPC3+C are set to '0'. the example above the start address of the VPC3+C is set to 1000H. Processor VPC3+ B DB[7..0] address AD[7..0]...
Figure 8-8: 80C32 Application in 4K Byte mode The internal chipselect is activated when the address inputs AB[10..3] of the VPC3+C are set to '0'. In the example above the start address of the VPC3+C is set to 2000H. Processor VPC3+ B DB[7..0]...
AB(10..0) Figure 8-10: 80C165 Application Dual Port RAM Controller The internal 4K Byte RAM of the VPC3+C is a single-port RAM. An integrated Dual-Port RAM controller, however, permits an almost simultaneous access of both ports (bus interface and microsequencer interface). When there is a simultaneous access of both ports, the bus interface has priority.
PROFIBUS Interface PROFIBUS Interface Pin Assignment The data transmission is performed in RS485 operating mode (i.e., physical S485). The VPC3+C is connected via the following signals to galvanically isolated in terface drivers. Signal Name Input/Output Function Output Request to send...
Figure 10-6: DC Specification of I/O Drivers for 3.3V Operation otes: For 3.3V operation the VPC3+C is equipped with 5V tolerant inputs except or the clock pin CLK. When using 3.3V supply voltage the clock input needs o be 3.3V level.
CLK. When using 3.3V supply voltage the clock input needs to be 3.3V level. Interrupt: After acknowledging an interrupt with EOI, the interrupt output of the VPC3+C is deactivated for at least 1 us or 1 ms depending on the bit EOI_Time_Base in Mode Register 0. Parameter Unit Interrupt inactive time EOI_Timebase = ‘0’...
In the asynchronous Intel mode, the VPC3+C acts like a memory with ready logic. The access time depends on the type of access. The request for an access to the VPC3+C is generated from the falling edge of the read signal (XRD) or the rising edge of the write signal (XWR).
Operational Specifications 10 10.7.4 Timing in the Synchronous Motorola Mode If the CPU is clocked by the VPC3+C, the output clock pulse (CLKOUT 2/4) must be 4 times larger than the E_Clock. That is, a clock pulse signal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse (E_Clock).
Ready logic, whereby the access times depend on the type of access. The request for an access of the VPC3+C is generated from the falling edge of the AS signal (in addition: XCS = '0', R_W = '1'). The request for a write access is generated from the rising edge of the AS signal (in addition: XCS = '0', R_W = '0').
The VPC3+C is a cracking-endangered component that must be properly handled. A drying process must be carried out before the VPC3+C is processed. The component must be dried for 24 hours at 125°C and then processed within 48 hours. Due to the solderability of the component this drying process may be carried out once only.
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