HP 83522A Service Notes page 237

Model 83522A
Service
First check the 200 kHz Clock. The SCAN CLK line is accessible at U3 pin 3, at
the top of the A3 assembly, so it is not necessary to remove the A3 board to test
it. The output frequency should be approximately 200 kHz. The pulse train is
NOT symmetrical, and has TTL levels. If no clock signal is found, suspect U3.
Error Code E053
If the SCAN CLK is present, yet E052 occurs, then the failure is probably with
U5. Press
S 5 , and check the LWR and LRD lines for the
waveforms shown in Figure 8-22. If either control line is inactive, troubleshoot
the address decoder U9. If the control lines are working, check the CTR 0 and
CTR 1 waveforms as shown in Figure 8-22. If they are incorrect, replace U5.
E053 generally indicates a failure in the PIA, U4. However, the problem might
be in the output stages of U5. Enter
SHIFT 5
S
, and check CTR 0 and
CTR 1 waveforms as shown in Figure 8-22. If they are correct, U5 is functional.
Next, check the L PIAE line as shown in Figure 8-22, and make sure the L
WRITE line shows activity. If not, troubleshoot the appropriate address
decoding circuitry or buffer. Then, check L PIIRQ for the squarewave shown in
Figure 8-22. If it is inactive, replace U4.
No Error Code
If no error code occurs and the 8350A displays show the correct start and stop
frequencies of the plug-in, the Plug-in Self Test passed successfully. This verifies
the Instrument Bus to the plug-in, data and address busses on the A3 Digital
Inteface assembly, and plug-in ROM. Any plug-in failures which are traced
back to the A3 assembly are due to failures in one or more of the following
areas:
Address Decoding
Plug-in Buffers
Interrupt Control/Configuration Switch
Miscellaneous Control Lines
If the 8350 displays show the wrong frequencies, first check configuration switch
Sl against Table 8-8, and then troubleshoot the PIA, U4.
Address Decoder
The primary address decoding for the plug-in occurs on the A3 assembly. The
enable lines are then passed on to the rest of the instrument. The Major Address
Decoder Test can be utilized to check all these lines. Enter:
SHIFT 5 3
Then check the outputs of U6B, U6C, U7B, U9, and U13 for the signals shown in
Figure 8-23. The address lines have been verified by the Self Test. Therefore, if
the LPIAE or ROM enable lines are faulty, troubleshoot the discrete address
decoding logic involving U6, U7, U8, and U10, and replace the defective
component. If other pulses are missing or displaced, replace the appropriate
decoder, U9 or U13.
Plug-In Interface
U14 and U17 buffer the address and data lines for use throughout the plug-in.
The address and data busses on the A3 assembly have been verified by the
Instrument Preset Self Test. Therefore, if address or data is not being passed to
another assembly, the fault lies with U14, U17, U6A, or a motherboard
connection.