Hexadecimal - HP 83522A Service Notes

Model 83522A
Table 8-3. Operator Initiated Self Test Routines Available
Service
By entering the Hex address location of a
specific device, that device can be exercised.
(Addresses are supplied next to the mnemonic
on each schematic. Also, circuit descriptions
usually include Address Decoder Tables to
define the addresses used on that particular
assembly.) A hex address entry must be made
prior to any of the following:
NOTE
Data Entry
SHIFT 50
SHIFT 51
SHIFT 52
SHIFT 53
SHIFT 54
SHIFT 55
Before addressing an 8 3 5 2 2 A component,
determine whether or not the 8 3 5 0 A
microprocessor can READ or WRITE t o that
particular device. The majority of 8 3 5 2 2 A
digital integrated circuits do NOT have both
READ and WRITE capabilities.
*Refer to troubleshooting procedure of the appropriate assembly for waveforms and detailed procedures.
?The address decoder for the A8 Sampler is on the A7 Marker Assembly.
Assembly*
A4
A5
A6
A3
A4, AS, A6,
A7, A8j-
A3
Test
Power Level DAC
Power Sweep DAC
ScalelOffset DACs
Address Decoder; checks major address decoder lines
Address Decoder; checks individual board address decoders
Interrupt Control
HEX DATA WRITE,
M2 , allows the
operator to write any combination of hex
data bytes to the addressed device. The
outputs can then be checked to see if the
device is functioning properly.
Test Point for Waveform
A4TP2
A5TP8
A6TP1 /A6TP2
A3U6, A3U7, A3U9, A3U13
Address Decoders
A3U4-38
HEX
DATA READ,
M3 ,
allows the
operator to read the outputs of an addressed
device.
HEX DATA ROTATION WRITE,
M4
,
strobes a '1' (high state) through a column
of zeroes (low states) to the addressed
device. In effect, Hex Data Rotation Write
is a rapid WRITE mode, exercising the
addressed device in real time. The micro-
processor inputs the data continuously,
without servicing interrupts from the rest of
the instrument. Latch enable lines, inputs,
and outputs can be checked in this mode.
Figure 8-2 illustrates the appropriate
waveforms.
HEX ADDRESSED FAST READ,
M5 ,
provides an operator-initiated check for
verification of the data bus, in which the
addressed device is clocked in real time.
Latch outputs can be traced from the
onboard location back throuh the data bus
to the microprocessor. At each buffer, verify
TI'L level response to the enable pulse.
Enable line waveforms are shown in Figure
8-3.
8-23. HEXADECIMAL
8-24. Hexadecimal is the number system used
to locally address the 8350A and 83522A logic
components. Available operator initiated self
test routines are indexed in Table 8-3.
8-25. The hexadecimal system uses 16 digits: 0
through 9 and A through F. Since 16 is the
fourth power of two, four-bit binary numbers
can be expressed with one hexadecimal digit,
making local programming easier. Table 8-4
provides hexadecimal conversions to binary and
decimal equivalents.