HP 83522A Service Notes page 243

Model 83522A
Service
The waveform in Figure 8-32 should be seen at TP2. Note that the exercise
routine for the 12-bit DAC yields a staircased waveform with 13 levels. The first
step shows the maximum
+
10 Vdc output with all bits high. The following levels
represent the voltage at TP2 with successive bits loaded high in order from the
Most Significant bit to the Least Significant Bit.
If the waveform at TP2 is not correct, check for -lOV REF, and trace any
problem back to the A6 assembly. Look for activity on L INST 1, BAO, and
BA1. BA2 and BA3 should pulse high as each new DAC value is loaded,
pulsing the CS line (U14 pin 8) low. If any of these lines, or a data line,
appears dead, trace the problem back to the A3 assembly.
U3A adds PWR SWP/COMP and AM, and provides detector flatness
compensation at higher power levels with CR2. Use the
EXT MTR
mode to
bypass these diodes while troubleshooting.
U3C adds the amplitude markers (L 1DB MKR) and the front panel amplitude
adjustment (EXT CAL) used with external leveling. The following levels should
be seen at TPl with A5 removed and
INT
leveling selected: +0.3 Vdc for -2
dBm, and +7.0 Vdc for +22 dBm. Amplitude markers produce a 250 mVdc dip
when the MKR light is on. An amplitude modulation (AM) signal of 1.0 Vp-p at
P1-4 will produce roughly 260 mV p-p at TP1.
Detector/Detector Selection Switch
@
DC1
The DCl detector is tested simply by checking its output voltages under full
leveled power or full unleveled power conditions. The A4 assembly must be
installed for troubleshooting as it supplies bias current to the detector.
NOTE
The 27.8 kHz modulation signal required for 8 7 5 5 compati-
bility is not available when the A4 assembly is removed from
the plug-in.
If no power is measured, turn off the line power and remove the A4
assembly. Return power to the instrument. (If there is still no RF power,
suspect components of the RF path. Refer to RF Troubleshooting.) If full
unleveled RF power is obtained, apply a narrow strip of cellophane tape to
the pin-edge connector to isolate the output of the PIN Mod 0 Driver from
the modulator (Pl-44). Reinstall the A4 board. This removes bias from the
modulator, allowing full RF power transmission, while providing detector
bias.
If full leveled power (4-13 dBm) or full unleveled power (at least 4-15 dBm) is
measured, sweep the full band and check the voltages at the detector inputs
against the values shown in Table 8-9. (Use high-impedance 10:l probes.)
Table 8- 9. Detector Voltages
If the detector is working and the Detector Selection Switch is suspected, sweep
the full band and monitor TP15 for the voltages seen at the selected input of
U6B.
Full Unleveled
**+20 dBm
-300 to -400 mV
A4P 1 -2 1
Full Leveled
+I 3 dBm
-150 to -200 mV