HP 83522A Service Notes page 189

A4 ALC TROUBLESHOOTING (CHANGE 8) (Cont'd)
Troubleshooting Diagnostics
The troubleshooting information below is organized into functional areas:
DIGITAL CONTROL A
REFERENCE POWER LEVEL C H
DETECTORS
/
DETECTOR SELECTION SWITCH By DCI
DETECTOR LEG E F G
MODULATORLEG I L
MOD DRIVER 0
MODULATOR
/
MIXER A17
DIGITAL CONTROL A
Address Decoder U12 and Control Latch U13 control digital switches throughout the
A4
assembly. Their operation can be confirmed by performing the Hex Data Rotation Write at
address 2C07 Hex. Enter the following keystrokes:
[SHITT] 1 0 1
lo1
Enters Hex Data command
121 [GHz
4
101
1 7 1
Address location 2C07 (U 1 3)
1 ~ 4 1
Hex Data Rotation Write
Check the outputs of U13 for the waveforms shown in Figure 8-2.
If any output signal is missing or misplaced, check the data lines agains Figure 8-2. If no
output is found, look for activity at U13 pin 11. Check for L INSTl and BA3 to pulse low,
while BAO, BAl, and BA2 pulse high. If these pulses are missing, trace the problem back to
A3 Digital Interface.
If the Digital Control Section is working, the primary outputs of U13 are easily controlled by
selecting the appropriate front panel function while in the CW sweep mode. (e.g. selecting
[MTR] leveling holds the PM line high, etc.)
REFERENCE POWER LEVEL C H
The Reference Power Level Leg produces a voltage proportional to the desired power level. This
signal is a summation of the absolute power reference, AM, RF plug-in amplitude markers, ALC
compensation, and power sweep signals.
The ALC compensation and power sweep signals are generated on the A% FM Driver assembly.
If an A5 failure is suspected, refer to troubleshooting information on the A5 Service Sheet.
Unless A5 is suspect, simplify A4 troubleshooting by turning off the line power and removing the
A5 assembly. Although power sweep will be disabled and the power flatness will be lost, the ALC
loop should still level without the signals provided by the A5 assembly.
DAC U11 establishes the absolute power level. The
-
10V REF from the A6 assembly is scaled to
yield from 0 Vdc
(
-
2 dBm displayed) to the
+
10 Vdc
(+
22 dBm displayed) at TP2. (This breaks
- -
7
down to a voltage step of 0 . 4 2 ~ d c per 1.0 dB of power over the dynamic range, or.6.25 Vdc at
+
13 dBm.
A self-test routine is available to exercise the ALC DAC. Enter:
[SHIFV
1 5 1 [OI
CHANGE 8