Mitsubishi MELSEC System Q Manual page 28

The CPU Modules
PLC CPUs
b Q00JCPU
CPU, power supply and a 5-slot base unit form an inseparable unit. Multi-CPU operation is
not possible with a Q00JCPU.
– Memory capacity for program: 8 k steps
– Execution time for a logical instruction: 0.2 µs
All of the following PLC CPUs are capable for Multi-CPU operation.
b Q00CPU
– Memory capacity for program: 8 k steps
– Execution time for a logical instruction: 0.16 µs
b Q01CPU
– Memory capacity for program: 14 k steps
– Execution time for a logical instruction: 0.10 µs
b Q02CPU
– Memory capacity for program: 28 k steps
– Execution time for a logical instruction: 0.079 µs
b Q02HCPU
– Memory capacity for program: 28 k steps (extendable with memory card)
– Execution time for a logical instruction: 0.034 µs
b Q06HCPU
– Memory capacity for program: 60 k steps (extendable with memory card)
– Execution time for a logical instruction: 0.034 µs
b Q12HCPU
– Memory capacity for program: 124 k steps (extendable with memory card)
– Execution time for a logical instruction: 0.034 µs
b Q25HCPU
– Memory capacity for program: 252 k steps (extendable with memory card)
– Execution time for a logical instruction: 0.034 µs
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The MELSEC System Q
MITSUBISHI ELECTRIC