Silicon Laboratories SiM3L1xx User Manual page 9

Table 3.2. Power Consumption
Parameter
Digital Core Supply Current
1,2,3,4
Normal Mode —Full speed
with code executing from flash,
peripheral clocks ON
1,2,3,4
Normal Mode —Full speed
with code executing from flash,
peripheral clocks OFF
1,2,3,4
Normal Mode —Full speed
with code executing from flash,
LDOs powered by dc-dc at 1.9 V,
peripheral clocks OFF
Notes:
1. Currents are additive. For example, where
functions increases supply current by the specified amount.
I
ncludes all peripherals that cannot have clocks gated in the Clock Control module.
2.
3. Includes LDO and PLL0OSC (>20 MHz) or LPOSC0 (<20 MHz) supply current.
4. Internal Digital and Memory LDOs scaled to optimal output voltage.
5. Flash AHB clock turned off.
6. Running from internal LFO, Includes LFO supply current.
7. LCD0 current does not include switching currents for external load.
8. IDAC output current not included.
9. Does not include LC tank circuit.
10. Does not include digital drive current or pullup current for active port I/O. Unloaded I
production test measurements.
Symbol Test Condition
I F = 49 MHz,
BAT AHB
F = 24.5 MHz
APB
F = 20 MHz,
AHB
F = 10 MHz
APB
F = 2.5 MHz,
AHB
F = 1.25 MHz
APB
I F = 49 MHz,
BAT AHB
F = 24.5 MHz
APB
F = 20 MHz,
AHB
F = 10 MHz
APB
F = 2.5 MHz,
AHB
F = 1.25 MHz
APB
I F = 49 MHz,
BAT AHB
F = 24.5 MHz
APB
V = 3.3 V
BAT
F = 49 MHz,
AHB
F = 24.5 MHz
APB
V = 3.8 V
BAT
F = 20 MHz,
AHB
F = 10 MHz
APB
V = 3.3 V
BAT
F = 20 MHz,
AHB
F = 10 MHz
APB
V = 3.8 V
BAT
I
is specified and the mode is not mutually exclusive, enabling the
BAT
Rev 1.1
Si M3 L 1 x x
Min Typ Max
— 17.5 18.9
— 6.7 7.2
— 1.15 1.4
— 13.3 14.5
— 5.4 5.9
— 980 1.2
— 9.7 —
— 8.65 —
— 4.15 —
— 3.9 —
is included in all I PM8
VIO BAT
Unit
mA
mA
mA
mA
mA
μA
mA
mA
mA
mA
9