Time sequence chart for the P_RESET FB
The figure below illustrates the behavior of the DONE and ERROR parameters depending
on the input circuit of REQ.
Figure 6-5
Note
The REQ input is edge-triggered. A positive edge at the REQ input is adequate. It is not
required that the RLO (result of logical operation) is "1" during the whole transmission
procedure.
PtP coupling and configuration of CP 340
Manual, 04/2011, A5E00369892-03
Time sequence chart for the P_RESET FB
Communication using function blocks
6.6 Delete receive buffer, FB12 "P_RESET"
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