Pioneer PDP-505HD Service Manual page 27

5
K2432
K2029
K2030
HOLD signal
generation circuit for
PLL control
K2408
Line
Number
Signal for detecting abnormal SYNC signal (Hi: in detecting)
Counter
Count value in the period of 1H by 16MHz clock (11-bit data)
Data is updated at the rate of HD1/8 dividing
HD Freq
Counter
K2019
K2018
Signal for detecting vertical frequency limit
Lo: Vertical frequency value is higher than
standard value (In PC input : fixed Hi)
Inverted PLL unlock information (Lo: When PLL is not locked)
SER-->PARA
CONV
K2031
Clamp & Blanking signal output from
Digital Assy
5
6
PLL output HD for A/D sampling &
clock SYNC reference
DIVOUT
HD_PLL
PLL input HD
HOLD controlling signal for comparing
PLL phase comparison.
HOLD_PLL
PLL unlock information
(Hi: When PLL is not locked)
ULK_PLL
Vertical line number count value (11-bit data)
Data is updated every 1 V sync.
LINE(0:10)
SYNC STATE
H_COUNT(0:10)
Timing signal for capturing horizontal frequency
count value (HD 1/8 dividing)
HD_U
VD_U
Vertical SYNC signal for
input signal detection
Serial Control sig
PLD_CE
DATA
CLK
VD_DSEL
VD SYNC signal sent to Digital Assy
CLP1
CLP2
HBLK1
VBLK2
6
7
AMP/AD/PLL IC
IC2402
(CXA3506R)
Signal Frequency DET
U-COM
IC2201
( PD2060A )
*Input signal detection
(stability)
*No signal input detection
*Detecting vertical frequency
*Controlling V_STD
(detecting frequency value)
K2027
Serial data
REQ_Su
V_STD
HOLD_Su
U-COM ASSY
DIGITAL VIDEO ASSY
7
8
PDP-505HD
1_2CLK
XCLK
HD_DSEL
Sending
*Data of vertical frequency
*Data of horizontal frequency
*Data of total numbers of lines
*Information on inapplicable
frequency
27
8
A
B
C
D