Block Diagram And Schematic Diagram - Pioneer PDP-505HD Service Manual

1
PDP-505HD

3. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM

3.1 OVERALL BLOCK DIAGRAM
CABLE ASSY
A
K2
SUS
OUT
5V 12V Vsus
Sustain
Pulse Gen.
IC3405
B
Vsus
+RST
OUT
+ Reset Pulse
Gen.
5V 12V Vsus
Sustain
Pulse Gen.
SUS
OUT
IC3402
X DRIVE ASSY
C
SIDE SW
S1
ASSY
IR
RECEIVE
ASSY
U1
D
K1 K2
CABLE ASSY
18
1
2
K1
SUS
5V
Logic
BLK
DRV
RST
Sig.
F7
5V
12V
PD
F6
OC
Vsus
F5
CONTROL ASSY
C4
S5V
REM
C1
SR SR
In
2
3
CABLE ASSY
K2 K1
MAIN POWER ASSY
P5
VSUS
P3
SW PWR SW PWR
DELAY
P6
HI PWR
OFF SW
P4
PD CONT
PD
PWR
STB5V
P1
5V
E3
Vadr
E35
E21 SDA
SCK
E24
E23
E18
Vsus
E1
E16
E17
E7
Vsus
5V
E8
Vadr
E12
E10
C2
LR
Tx
Rx
Out
K2
K1
CABLE ASSY
3
4
CABLE ASSY
K2 K1
OC
OVC
VADR
VCC
SW PWR
+B
DELAY
PFC
PD
Relay
STB12V
FU101
STBY
PWR
P7
AC IN
E5
12V
E6
5V
E2
E19
PWR
S5V
RST
14V
R5V S5V
5V
REG
SYSTEM
CONT CPU
DAT, CLK
IC3604
SDet, FDet
REM, Tx, Rx,Vol, Mute
E15
U-COM ASSY
KEY, LED
A33
A19
A20
IC2402
SDet AMP/AD/PLL
DAT
CLK
A1
HD
HD,VD
A2
Sync
Sync
U-Com
SEL
F-DET
A3 CONT
CLP,HV
BLK
P&P
A5
RGB
In
IN 4
K1 K2
CABLE ASSY
4
D13
D1
RGB
D19
DAT
IP
Process
D4
CLP Pulse
Gen.
D18
CL
D12
D
D20 D22
Vadr
14V 14V
R10V
REG
E2
FAN
FAN
CONT
DRV
BLK
E3
FAN
MAX
SD
SENS
EEPROM
IC3601
LED
E2
Vadr
E34
9V_PIC
5APLL -
A35
12V
A17 9V_SIG
5VBPLL
RE
V.ROM
YCbC
RGB
RGB
YPbP
Decoder
RGB
IC1401
CLP,HV
Y
BLK
YPbPr
G/Y
HDVD
Sync
Sepa
Sync
SEL
In3/In4
HD
SEL
VD
VD C
G B HD
R
Pr Y Pb CS
IN 3