Pioneer PDP-505HD Service Manual page 26

1
PDP-505HD
3.4 SYNC SIGNAL PROCESSING BLOCK
A
Control signal for switching
mask width (Lo : In PC input)
Noise cancel processing
Limit to U-com processing
velocity (Max: 200Hz)
HD/VD SYNC signal selected by input function
for generating Mask pulse
(except for when selecting HD_PLD, VD_PLD)
B
Input from IC1201
(Jungle-IC)
in Comp/S input
(Positive polarity)
Separate HD/CS,
VD SYNC signal
input from BNC/D-
sub 15p
C
Y/G ON SYNC signal
SYNC_SEPA
in inputting Y color-
difference or RGB
signals
D
Clamp & Blanking pulse
output to Analog Video
block
26
1
2
Noise cancel processing
Countermeasure for copy guard
Limit to U-com processing velocity
(Max: 200kHz)
IC2004(2/2)
TC74VHC123
MASK_DSW
IC2004(2/2)
TC74VHC123
K2020
K2021
K2033
HD_PLD
K2032
VD_PLD
K2023
HD_3
K2025
HD_4
K2024
VD_3
K2026
VD_4
K2004
4pin
SYNC SEPA IC
IC2002
(M52346S)
K2012
CLP_AMP
K2015
CLP_MAT
K2013
HBLK_MAT
K2014
VBLK_MAT
2
3
HD_MASK
VD_MASK
VD_FIL
HD_FIL
SYNC signal output
separated from Y/G
ON SYNC signal
14pin
HD_+
15pin
HD_–
13pin
VD_+
6pin
HD_SEP
8pin
VD_SEP
Selected HD/VD signal
used for Separate input
SYNC signal detection
2pin
HSTATE
1 pin
VSTATE
18pin
HPOL
19pin
VPOL
Information on detecting Separate
input SYNC signal & the polarity
CLP_SW1,2
CLP_SEP (Switching
Clamp pulse width
Clamp pulse generated by SYNC
Separate IC (Used in PC input)
17pin
CLP_SEPA
3
4
SYNC CONTROL PLD
IC2005(PDY069)
Noise
Mask
Gate
Noise
Mask
Gate
SYNC signal selected based on
input function & HD/VD signal
detected (Unify the polarity to
negative polarity)
Signal
selector for
SYNC signal
&
Circuit for
switching
polarity
Decoding
HD/VD signal
detected
20 bit /
Parallel
data
CONTROL
LOGIC
Selecting input
SYNC signal
Setting value of
HOLD Pulse width
CLAMP/
BLANKING
PULSE
CONTROL
4