Main Unit - Icom IC-7300 Service Manual

3-3 MAIN UNIT

The IC-7300 uses the Direct Conversion system, which di-
rectly converts the received signal into a digital signal by the
A/D converter. The digital signal is then converted into the 36
kHz IF signal by the FPGA, before being processed by the
DSP.
The transmit signal is processed and converted into the
transmit IF signal by the DSP. The transmit IF signal is con-
verted into an RF signal by the FPGA, and then converted
into an analog transmit signal. Since the IF signal is directly
processed as a digital signal in the FPGA, any analog hetero-
dyne circuits, such as IF circuits, are not needed.
(1) RECEIVE SIGNAL PROCESSING
• External attenuator and A/D conversion
The received signal from the RF UNIT is passed through the
TX/RX switching diode (D1231) and applied to the external
attenuator (PIN diode D1251). The attenuator is controlled by
the AGC voltage from the D/A converter (IC971) to adjust the
received signal level so that the signal amplitude is within the
input dynamic range of the A/D converter.
• MAIN UNIT (Receive circuits)
J1302
1.8V
1
2.GND
2
3.HSEND
3
4.START
4
5.BAND
5
6.ALC
6
7.NC
[ACC] 7
8.14V
8
9.KEY
9
10.FSKK
10
11.MOD
11
12.AF 12
13
13.SQLS
L731,L732
Q746 C731~C735
J101
SW
SP1
TX signal
RX signal
IC901
DSP
FPX_AGC/FPX_DET/FPR_MOD
/FPCAL/BCLK/FRM/MCLK
IC991
IC992
AAF
AF
AMP
IC721 IC992
AF AF
LPF
AMP AMP
DISPLAY UNIT MIC UNIT
MICE
MIC
GND
AF OUT
+8V
2
PTT
SQL
MIC U/D
PHONE UNIT
AFO
In a traditional transceiver, the received signal level (gain)
was controlled by the DSP prior to the external AGC circuit.
But, this method will not work in the Direct Sampling system
since the RF gain control cannot prevent over input to the
A/D converter. This method has been replaced by adding an
external AGC circuit, instead of using the DSP's internal AGC
circuitry.
The level-adjusted received signal is applied to the A/D con-
verter to be converted into a digital signal. The converted digi-
tal signal is applied to the FPGA (IC1351) where the received
signal is converted into the 36 kHz IF signal.
IC1351
DACLK
FPGA
IC1212
D/A
LVDS
DRIVE
41.344 MHz
D/A
J1
1 7
8 6
3 5
4
J1
3-4
IC1331
D/A
IC1221
XTAL 124.033 MHz
AMP
BPF
D1251
PIN
A/D
ATT
AGCV
IC971
D/A
Q1201
Q1202
IC1211
X1201
AMP BUFF
(41.344 MHz)
MAIN UNIT
LPF
D1231
RF