Pll Circuits - Icom IC-R5 Service Manual

(2) WFM mode
The 3rd IF signal from the 3rd mixer bypasses the ceramic fil-
ter (FI2) and fed back to the limiter amplifier section (pin 5).
The amplified signal is demodulated at the quadrature detec-
tor section (pins 10, 11) and detector coil (L21). The AF sig-
nals are output from pin 9 and are applied to the AF circuit
(LOGIC unit) via the "FMDET" signal.
By connecting R55 to R54 in parallel, the output characteris-
tics of pin 12, "RSSI", change gradually. Therefore, the FM IF
IC can detect WFM components.
(3) AM mode
The filtered 3rd IF signal from the bandpass filter (FI2) is
amplified at the 3rd IF amplifier (Q1). The amplified IF signal
is applied to the AM detector circuit (Q4) to converted into AF
signals, and the signals are applied to the AF circuit (LOGIC
unit) via the "AMDET" signal.
4-1-6 AF AMPLIFIER CIRCUIT (LOGIC UNIT)
The AF amplifier circuit amplifies the demodulated AF signals
to drive a speaker.
While in FM mode, AF signals from the demodulator circuit
(RF unit) are passed through the de-emphasis circuit (R323,
C316, C318) with frequency characteristics of –6 dB/octave,
and are then applied to the pre-amplifier (Q300) via the high-
pass filter (Q301).
While in AM mode, AF signals are pass through the high-
pass filter (Q301) and are then applied to the pre-amplifier
(Q300).
While in WFM mode, AF signals are applied to the pre-ampli-
fier (Q300) directly via the mode swtich (Q302).
The pre-amplified AF signals pass through the AF mute cir-
cuit (Q350) and are then applied to the electronic volume
control circuit (IC400, pin 6). The level controlled AF signals
are output from pin 7 and applied to the AF power amplifier
(Q452 and IC450, pin 1) via the buffer amplifier (Q400). The
power amplified AF signals are applied to the internal speak-
er via the [EXT SP] jack.
• PLL CIRCUIT
"SHIFT" signal from CPU
(LOGIC unit; IC1, pin 62)
Loop
Q2,
Q45
to the FM IF IC
(IC2, pin 2)
19.2 MHz
Shift
switch
Q29, D46
1st VCO
Q28, Q30, D54
filter
Phase
13
detector
17 Programmable
divider
X1 16
The electronic volume control circuit controls AF gain, there-
fore, the AF output level is according to the [VOL] setting and
also the squelch conditions.
4-1-7 SQUELCH CIRCUIT (LOGIC AND RF UNITS)
• NOISE SQUELCH
The noise squelch circuit cuts out AF signals when no RF sig-
nals are received. By detecting noise components in the AF
signals, the squelch circuit switches the AF mute switch.
A portion of the "NOISE" signals from the FM IF IC (RF unit;
IC2, pin 13) are applied to the CPU (LOGIC unit; IC1, pin 47).
The CPU analyzes the noise condition and outputs the
"AMUTE" signal (from pin 50) to the AF mute switch (LOGIC
unit; Q350).
• TONE SQUELCH
The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS). When tone squelch is in use, and
a signal with a mismatched or no subaudible tone is
received, the tone squelch circuit mutes the AF signals even
when noise squelch is open.
A portion of the AF signals from the FM IF IC (IC2, pin 9)
passes through the low-pass filter (LOGIC unit; IC200, pin 5)
via the "FMDET" line to remove AF (voice) signals and is
applied to the CTCSS decoder inside the CPU (LOGIC unit;
IC1, pin 7) via the "RTONE" line to control the AF mute
switch.

4-2 PLL CIRCUITS

4-2-1 PLL CIRCUIT (RF UNIT)
A PLL circuit provides stable oscillation of the receive 1st/2nd
LO frequencies. The PLL circuit compares the phase of the
divided VCO frequency to the reference frequency. The PLL
output frequency is controlled by the divided ratio (N-data) of
a programmable divider.
Buffer
Q40
Buffer
IC4
Buffer
Q43
IC3 (PLL IC)
Programmable
19
Prescaler
counter
3
4
Shift register
5
4 - 3
to 1st mixer circuit
PSTB
PCK
PDAUL