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%WWMKRQIRX SJ .4 '3 GSRRIGXSV
A.1.1.3
Pin
MPC pin
Signal name
2
A15
BAN51_PQB7
4
B14
BAN52_PQA0
6
C13
BAN53_PQA1
8
B15
BAN54_PQA2
10
D13
BAN55_PQA3
12
C14
BAN56_PQA4
14
C15
BAN57_PQA5
16
D14
BAN58_PQA6
18
D15
BAN59_PQA7
26
H2
B_TPUCH0
27
K20
A_CNRX0
28
H1
B_TPUCH1
29
K19
A_CNTX0
30
G1
B_TPUCH2
32
G2
B_TPUCH3
33
H3
B_CNRX0
34
G3
B_TPUCH4
35
H4
B_CNTX0
36
F1
B_TPUCH5
38
F2
B_TPUCH6
39
M20
SCK_QGP6
40
E1
B_TPUCH7
41
L19
MISO_QGP4
42
F3
B_TPUCH8
44
G4
B_TPUCH9
45
L20
MOSI_QGP5
46
E2
B_TPUCH10
47
L18
PCS0_QGP
48
D1
B_TPUCH11
50
F4
B_TPUCH12
51
L17
PCS1_QGP
52
D2
B_TPUCH13
53
M18
PCS2_QGP
54
E3
B_TPUCH14
56
C1
B_TPUCH15
57
M17
PCS3_QGP
58
B1
B_T2CLK
62
J19
VF0_MPIO0
64
J20
VF1_MPIO1
66
J17
VF2_MPIO2
67
J18
VFLS0_MPIO3
69
K18
VFLS1_MPIO4
71
L2
IWP0_VFLS
73
L1
IWP1_VFLS
MOTOROLA
A-32
Description corresponding to the data sheet
See AAN48_PQB4
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
See AAN52_PQA0
B_TPUCH0 - B_TPUCH15: Time Processor Unit B channel
TOUCAN receive data 0: serial data input
See B_TPUCH0
TOUCAN transmit data 0: serial data output
See B_TPUCH0
See B_TPUCH0
TOUCAN receive data 0: serial data input
See B_TPUCH0
TOUCAN transmit data 0: serial data output
See B_TPUCH0
See B_TPUCH0
SCK: provides the clock from the QSPI in master mode or to the QSPI in
slave mode
See B_TPUCH0
Master-in slave-out (MISO): provides serial data input to the QSPI in
master mode and serial data output from the QSPI in slave mode
See B_TPUCH0
See B_TPUCH0
Master-out slave-in (MOSI): provides serial data output to the QSPI in
master mode, and serial data input from the QSPI in slave mode.
See B_TPUCH0
PCS0: provide QSPI peripheral chip select 0.
SS: places the QSPI in slave mode.
QSPI GPIO[0]: can be configured as GPIO if not needed.
See B_TPUCH0
See B_TPUCH0
PCS1: provide QSPI peripheral chip select 1.
QSPI GPIO[1]: can be configured as GPIO if not needed.
See B_TPUCH0
See PCS1_QGP
See B_TPUCH0
See B_TPUCH0
See PCS1_QGP
See A_T2CLK
VF[0:2] visible instruction queue flush status: output by the chip when pro-
gram instruction flow tracking is required. GPIO
See VF0_MPIO0
See VF0_MPIO0
Visible history buffer flush status: to allow program instruction flow
tracking.
See VFLS0_MPIO3
Instruction watchpoint. Visible history buffer flush status: output by the
chip to enable program instruction flow tracking.
See IWP0_VFLS
EVB555
Quick Reference
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