Motorola EVB555 Quick Reference page 18

Bit
0
1
2
3
4:5
9:10
11
12
13:14
16
17:18
19
20
23
28:30
31
MOTOROLA
4-20
Name Description
0: internal arbitration
EARB
1: external arbitration
Interrupt table location after reset
IP 0: MSR(IP) =1
1: MSR(IP) =0
0: reduced drive strength of bus pins
BDRV
1: full drive strength of bus pins
0: bank 0 is bootable
BDIS
1: memory controller inactive
Boot port size
00: 32-bit
BPS 01: 8-bit
10: 16-bit
11: reserved
Debug pin configuration (IWP,BI,BG,BR,BB)
DBGC
(6.13.1.1)
Debug pin configuration
DBPC 0: BDM
1: JTAG
Address type <> Write enable
ATWC
0: /WE
External bus division factor
EBDF 00: CLKOUT = GCLK2
01: CLKOUT = GCLK2/2
Peripheral mode enable
PRPM 0: normal
1: external master
Single chip select
00: extended chip, 32-bit data
SC 01: extended chip, 16-bit data
10: single chip, show cycle (address)
11: single chip
Extended table relocation
ETRE
0: off
0: internal flash disabled (boot external)
FLEN
1: internal flash enabled
0: little endian swap logic inactive
CLES
1: little endian swap logic active
ISB Initial internal space base (6.12.1.2)
0: dual mapping disabled
DME
1: dual mapping enabled
Table 4-1 Hard reset configuration word
1: AT
1: on
Var. 1
0
0
1
0
00
10
0
0
00
0
00
0
1
0
00
0
EVB555
Quick Reference