Table of Contents
Advertisement
A.1.1.2 Assignment of J2/P2 (CO601) connector:
Pin
MPC pin
Signal name
2
D9
AAN50_PQB6
4
B9
AAN49_PQB5
6
A9
AAN48_PQB4
8
B8
AAN3_PQB3
10
C8
AAN2_PQB2
12
14
A8
AAN0_PQB0
21
A17
MDA11
22
A18
MDA12
23
A19
MDA13
24
B17
MDA14
25
B18
MDA15
26
C17
MDA27
27
B20
MDA28
28
C18
MDA29
30
W20
/HRESETB
31
C16
ETRIG1
32
U18
EXTCLK
33
B16
ETRIG2
34
N4
/BBB_IWP3
35
U4
/BDIPB
36
N3
/BGB_LWP1
37
V2
/BIB_/STSB
38
N2
/BRB_IWP2
39
V1
/BURSTB
40
M4
SGP_/IRQOUTB
41
U3
/TSB
42
P18
EPEE
47
M19
ECK
48
U19
ENGCLK/BUCLK
49
N17
RXD1_QGPI
50
N18
TXD1_QGPO
51
N19
RXD2_QGPI
52
N20
TXD2_QGPO
61
C19
MDA30
65
C20
MDA31
66
G17
MPIO5
67
E20
MPIO6
MOTOROLA
A-30
Description corresponding to the data sheet
See AAN48_PQB4
See AAN48_PQB4
Analog input channel: passed on as a separate signal to the QADC.
Port (PQB): has a synchronizer with an input enable and clock.
See AAN0_PQB0
See AAN0_PQB0
See AAN0_PQB0
Multiplexed input analog channel: passed on as a
separate signal to the QADC.
Double action: provide a path for two 16-bit input captures
and two 16-bit output captures.
See MDA11
See MDA11
See MDA11
See MDA11
See MDA11
See MDA11
See MDA11
Hard reset: after negation of /HRESET is detected, a 16-cycle period is
taken before testing an external reset. An external pull-up device is
required to negate /HRESET.
External trigger input to the QADC_A and QADC_B modules.
Can be configured for both QADC_A and QADC_B.
External frequency source for the chip.
Must be grounded if unused.
See ETRIG1
Bus busy: master is using the bus.
Visible instruction queue flush status.
Load/store watchpoint. 3
Burst data in progress: indicates that a data beat follows the current one.
Bus grant: indicates external data bus status. Visible instruction
queue flush status Load/store watchpoint
Burst inhibit: "0" → slave device is not able to support burst transfers.
Special transfer start: beginning of an internal transaction in showcycle
mode.
Bus request: the data bus has been requested for external cycle.
Visible instruction queue flush status Load/store watchpoint 2
Burst indicator: "0" → burst transaction
SGPIO, interrupt out: an interrupt has been sent to external devices.
Transfer start: start of a bus cycle that transfers data
Input: will externally control the program or erase operations.
External bus clock (EBCK): external baud clock used by SCI1 and SCI2
ENGCLK: engineering clock output. Full strength, half strength, disabled.
Using EECLK[0:1] bits in the SCCR register.
BUCLK: backup clock, less precise on-chip ring oscillator for minimum
functionality.
Receive data: serial input from the SCI1
Transmit data: serial output from the SCI1
Receive data: serial input from the SCI2
Transmit data: serial output from the SCI2
See MDA11
See MDA11
GPIO
GPIO
EVB555
Quick Reference
Advertisement
Table of Contents
