Power4 And Power5 Architecture Comparison - IBM p5 590 System Handbook

shared second-level (L2) cache, a directory for an off-chip third-level (L3) cache,
and the necessary circuitry to connect it to other POWER4 chips to form a
system. The dual-processor chip provides natural thread-level parallelism at the
chip level.
The POWER5 microprocessor is IBMs second generation dual core
microprocessor and extends the POWER4 design by introducing enhanced
performance and support for a more granular approach to computing. The
POWER5 chip features single- and multi-threaded execution and higher
performance in the single-threaded mode than the POWER4 chip at equivalent
frequencies.
The primary design objectives of the POWER5 microprocessor are:
Maintain binary and structural compatibility with existing POWER4 systems
Enhance and extend symmetric multiprocessing (SMP) scalability
Continue to provide superior performance
Deliver a power efficient design
Enhance reliability, availability, and serviceability
POWER4 to POWER5 comparison
There are several major differences between POWER4 and POWER5 chip
designs, and they include the following areas shown in Figure 1-3, and as
discussed in the following sections:
POWER4+ to POWER5 comparison
POWER4+ design
L1 cache
L2 cache
L3 cache
Simultaneous
multi-threading
Partitioning support
Floating-point rename
registers
Chip interconnect:
Type
Intra MCM data bus
Inter MCM data bus
Size
Figure 1-3 POWER4 and POWER5 architecture comparison
POWER5 design
2-way associative 4-way associative
8-way associative 10-way associative
1.5MB 1.9MB
32MB 36MB
8-way associative 12-way associative
118 clock cycles Reduced latency
No Yes
1 processor
th
1/10 of processor
72 120
Distributed switch Enhanced dist. switch
½ proc. speed Processor speed
½ proc. speed ½ proc. speed
412mm 2 389mm 2
Benefit
Improved L1 cache
performance
Fewer L2 cache misses
Better performance
Better cache performance
Better processor utilization
30%* system improvement
Better usage of processor
resources
Better performance
Better systems throughput
Better performance
50% more transistors in
the same space
* Based on IBM rPerf projections
Chapter 1. System overview
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