IBM p5 590 System Handbook page 44

Reference Platform (CHRP) specifications. Figure 2-2 on page 24 shows the
POWER chip evolution.
POWER4
POWER4 processor is not just a chip, but rather an architecture of how a set
of chips is designed together to build a system. As such, POWER4 can be
considered a technology in its own right. The interconnect topology, referred
to as a Distributed Switch, was new to the industry with POWER4. In that
light, systems are built by interconnecting POWER4 chips to form up to
32-way symmetric multi-processors. The reliability, availability, and
serviceability design incorporated into POWER4 is pervasive throughout the
system and is as much a part of the design. POWER4 is the chip technology
used in the pSeries Models 615, 630, 650, 655, 670, 690, and IntelliStation
275. It is also the basis for the PowerPC® 970 used in JS20 BladeCenter™
servers.
The POWER4 design can handle a varied and robust set of workloads. This is
especially important as the on demand business world evolves and data
intensive demands on systems merge with commercial requirements. The
need to satisfy high performance computing requirements with its historical
high bandwidth demands and commercial requirements, along with data
sharing and SMP scaling requirements dictate a single design to address
both environments.
POWER5
POWER5 technology is the next generation of IBM 64-bit architecture.
Although the hardware is based on POWER4, POWER5 is much more than
just an improvement in processor or chip design. It is a major architectural
change, creating a much more efficient superscalar processor complex. For
example, the high performance distributed switch is enhanced. POWER5
technology is implemented in the Sserver p5 Models 510, 520, 550, 570,
575, 590, 595 and the OpenPower™ 710 and 720 systems.
As with POWER4 hardware technology, POWER5 technology-based
processors have two load/store, two arithmetic, one branch execution unit,
and one execution unit for logical operations on the cycle redundancy (CR).
The design of the processor complex is such that it can most efficiently
execute multiple instruction streams concurrently. With simultaneous
multi-threading active, instructions from two different threads can be issued
per single cycle.
The POWER5 concept is a step further into autonomic computing
enhanced reliability and availability enhancements are implemented. Along
with increased redundant components, it incorporates new technological high
2
Autonomic computing: An approach to self-managed computing systems with a minimum of human
interference. The term derives from the body's autonomic nervous system, which controls key
functions without conscious awareness or involvement.
IBM Eserver p5 590 and 595 System Handbook
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2
. Several