7Deoh  0Xowlso\ /Lvwlqj - ZiLOG Z80 User Manual

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7DEOH  %XEEOH /LVWLQJ &RQWLQXHG
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2EM &RGH 6WPW 6RXUFH 6WDWHPHQW
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7KH IROORZLQJ SURJUDP VHH 7DEOH  PXOWLSOLHV WZR XQVLJQHG ELW
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7DEOH  0XOWLSO\ /LVWLQJ
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0000
80
43
flag: equ
44
data: defs
45
end
2EM
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6WPW 6RXUFH 6WDWHPHQW
1
mult:; unsigned sixteen bit integer multiply.
2
;
3
;
4
;
5
;
6
;
7
;
8
;
9
;
10
;
11
;
12
;
13
;
14
;
15
;
+DUGZDUH DQG 6RIWZDUH ,PSOHPHQWDWLRQ ([DPSOHV
0
; designation of flag bit
2
; storage for data address
on entrance: multiplier in de.
multiplicand in hl.
on exit result in hl.
register uses:
h
high order partial result
l
low order partial result
d
high order multiplicand
e
low order multiplicand
b
counter for number of shifts
c
high order bits of multiplier
< %27
7UGT U /CPWCN


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