Ljxuh  = ,2 3Lq &Rqiljxudwlrq - ZiLOG Z80 User Manual

System
Control
CPU
Control
CPU
Bus
Control
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Address Bus (output, active High, tristate). A15-A0 form a 16-bit address
bus. The Address Bus provides the address for memory data bus
exchanges (up to 64 Kbytes) and for I/O device exchanges.
80
27
M1
19
MREQ
20
IORQ
21
RD
22
WR
28
RFSH
18
HALT
24
WAIT
16
INT
17
NMI
26
RESET
25
BUSRQ
23
BUSACK
6
CLK
11
+5V
29
GND
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Z80 CPU
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30
A0
31
A1
32
A2
33
A3
34
A4
35
A5
36
A6
37
A7
Address
38
Bus
A8
39
A9
40
A10
1
A11
2
A12
3
A13
4
A14
5
A15
14
D0
15
D1
12
D2
8
D3
Data
7
D4
Bus
9
D5
10
D6
13
D7
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