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Last M Cycle of Instruction
CLK
INT
A — A
15 0
M1
MREQ
IORQ
D — D
7 0
WAIT
RD
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Figure 10 illustrates the request/acknowledge cycle for the non-maskable
interrupt. This signal is sampled at the same time as the interrupt line, but
this line takes priority over the normal interrupt and it can not be disabled
under software control. Its usual function is to provide immediate
response to important signals such as an impending power failure. The
CPU response to a non-maskable interrupt is similar to a normal memory
read operation. The only difference is that the content of the data bus is
ignored while the processor automatically stores the PC in the external
stack and jumps to location
maskable interrupt must begin at this location if this interrupt is used.
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Last T State
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. The service routine for the non-
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