Kenwood TK-250 Service Manual page 20

TK-250
CIRCUIT DESCRIPTION
5. PLL FREQUENCY SYNTHESIZER
5.1 PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A
12.8MHz reference oscillator signal is divided at IC3 by a
fixed counter to produce the 5 or 6.25kHz reference fre-
quency. The VCO output signal is buffer amplified by 013,
then divided in IC3, by a dual-modules programmabie counter
in this case. The divided signal is compared in phase with
the 5 or 6.25kHz reference signal in the phase comparator
also in IC3. The output signal from the phase comparator is
low-pass filtered and passed to the VCO to control the oscil-
lator frequency.
5.2 Voltage controlled oscillator(VCO)
The operating frequency is generated by 0504 in transmit
mode and 0505 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained from
the phase comparator , to the varactor diodes ( 0501 in
transmit mode and 0502 and 0503 in receive mode). The
TI
R pin in set high in receive mode causing 0501 and 0502 to
turn off 0504, and turn on 0505, and is set low for transmit
mode. The outputs from 0504 and 0505 are amplified by
0503 and outputed to the buffer amplifiers.
5.3
Unlock detector
If a pulse signal appears at the LO pin of IC3, an unlock
condition occurs , the OC voltage obtained from 09 and
011, causes the voltage applied to the UL pin of the micro-
processor to go low. Wh en the microprocessor detects this
condition, the transmitter is disabled by ignoring the push-
to-talk switch input signa!.
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Fig.6 PLL frequency synthesizer
20