Sony STR-DA5400ES Service Manual page 133

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Pin No. Pin Name
H14 DPDVBCK
J1, J2 AD5, AD4
J4 to J6,
J9 to J11
J13
J14 DPDVLRCK
K1
K2
K4 to K6,
K9 to K11,
K13
K14
L1, L2 AD2, AD1
L4 to L6,
L9 to L11,
L13
L14
M1
M2
M3, M12
M13
M14
TE
L 13942296513
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11, N12
N13
N14
P1 to P6 AD14 to AD9
P7
P8
P9 SF2_DSP2_MAS
P10
P11
P12
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P13
.
P14
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I/O
Bit clock signal output for PCM audio signal output to the lip sync adjust and D/A converter
(for audio section) (US and Canadian models)
O
Bit clock signal output for PCM audio signal output to the fi eld programmable gate array
(AEP, Continental European, East European, Russian and UK models)
I/O Two-way data bus with S-RAM and address signal output to the address latch
GND - Ground terminal
VDDINT - Power supply terminal (+1.2V)
L/R sampling clock signal output for PCM audio signal output to the lip sync adjust and D/A
converter (for audio section) (US and Canadian models)
O
L/R sampling clock signal output for PCM audio signal output to the fi eld programmable gate
array (AEP, Continental European, East European, Russian and UK models)
AD3 I/O Two-way data bus with S-RAM and address signal output to the address latch
VDDINT - Power supply terminal (+1.2V)
GND - Ground terminal
DPSIE I PCM audio signal (surround back L/R) input from the DSP1
I/O Two-way data bus with S-RAM and address signal output to the address latch
GND - Ground terminal
DPSID I PCM audio signal (center, sub woofer) input from the DSP1
AD0 I/O Two-way data bus with S-RAM and address signal output to the address latch
WR O Data write enable signal output to the S-RAM
GND - Ground terminal
DPSIB I PCM audio signal (front L/R) input from the A/D converter, HDMI receiver or DSP1
DPSIC I PCM audio signal (surround L/R) input from the DSP1
AD15 O Address signal output to the S-RAM and address latch
ALE O Address latch enable signal output to the address latch
RD O Data read enable signal output to the S-RAM
VDDINT - Power supply terminal (+1.2V)
VDDEXT - Power supply terminal (+3.3V)
AD8 O Address signal output to the S-RAM and address latch
VDDINT - Power supply terminal (+1.2V)
DAI_P2 - Not used
VDDEXT - Power supply terminal (+3.3V)
DAI_P4 I Degital audio signal input from the DSP1
VDDINT - Power supply terminal (+1.2V)
GND - Ground terminal
DPSOE O PCM audio signal output terminal
O Address signal output to the S-RAM and address latch
DAI_P1 O Address signal output to the S-RAM
DAI_P3 - Not used
O Master/slave mode selection signal output terminal
PCM audio signal (front L/R) output to the lip sync adjust (US and Canadian models)
DPSOA O PCM audio signal (front L/R) output to the fi eld programmable gate array
(AEP, Continental European, East European, Russian and UK models)
PCM audio signal (surround L/R) output to the lip sync adjust (US and Canadian models)
DPSOB O PCM audio signal (surround L/R) output to the fi eld programmable gate array
(AEP, Continental European, East European, Russian and UK models)
PCM audio signal (center, sub woofer) output to the lip sync adjust
(US and Canadian models)
DPSOC O
PCM audio signal (center, sub woofer) output to the fi eld programmable gate array
(AEP, Continental European, East European, Russian and UK models)
PCM audio signal (surround back L/R) output to the lip sync adjust
x ao
(US and Canadian models)
y
DPSOD O
PCM audio signal (surround back L/R) output to the fi eld programmable gate array
i
(AEP, Continental European, East European, Russian and UK models)
DPSIA I PCM audio signal (digital input) input from the DSP1
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8
Q Q
3 6 7 1 3
Not used
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STR-DA5400ES
2 9 9 4 2 8
Description
1 5 0 5 8 2 9 9 4
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9 9
2 8 9 9
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