Sony STR-DA5400ES Service Manual page 132

STR-DA5400ES
QQ
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DSP BOARD IC5202 ADSST-AVR-1131 (DSP2)
Pin No. Pin Name
A1 CLKCFG0
A2 XTAL
A3 TMS
A4 TCK
A5 TDI
A6 CLKOUT
A7 TDO
A8 EMU
A9 MOSI
A10 MISO
A11 SPIDS
A12 VDDINT
A13, A14 GND
B1 CLKCFG1
B2 GND
B3 VDDEXT
B4 CLKIN
B5 TRST
B6 AVSS
B7 AVDD
B8 VDDEXT
B9 SPICLK
TE
L 13942296513
B10 RESET
B11 VDDINT
B12 to B14 GND
BOOTCFG1,
C1, C2
BOOTCFG0
C3, C12,
GND
C13
C14, D1 VDDINT
D2,
D4 to D6,
GND
D9 to D11,
D13
D14, E1 VDDINT
E2,
E4 to E6,
GND
E9 to E11,
E13
E14 SF2_DSP2_CE
F1 FLAG1
F2 FLAG0
F4 to F6,
GND
F9 to F11
F13 P_ERROR
F14 DPFSCK
G1 AD7
G2 VDDINT
G13 VDDEXT
www
G14 DPBCK
H1 AD6
.
H2 VDDEXT
H13 DPLRCK
132
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I/O
I Clock frequency setting terminal
O System clock output terminal (25 MHz)
I Mode selection signal input terminal (for JTAG)
I Clock signal input terminal (for JTAG)
I Data input terminal (for JTAG)
O Clock signal output terminal
O Data output terminal (for JTAG)
- Not used
When DSP2 is master: Serial data output to the serial fl ash
I/O
When DSP2 is slave: Serial data input from the DSP controller
When DSP2 is master: Serial data input from the serial fl ash
I/O
When DSP2 is slave: Serial data output to the DSP controller
I Serial data latch pulse signal input from the DSP controller
- Power supply terminal (+1.2V)
- Ground terminal
I Clock frequency setting terminal
- Ground terminal
- Power supply terminal (+3.3V)
I System clock input terminal (25 MHz)
I Reset signal input terminal (for JTAG)
- Ground terminal
- Power supply terminal (+1.2V)
- Power supply terminal (+3.3V)
When DSP2 is master: Serial data transfer clock signal input from the DSP controller
I/O
When DSP2 is slave: Serial data transfer clock signal output to the serial fl ash
I Reset signal input from the DSP controller
- Power supply terminal (+1.2V)
- Ground terminal
I Boot mode setting signal input from the DSP controller
- Ground terminal
- Power supply terminal (+1.2V)
- Ground terminal
- Power supply terminal (+1.2V)
- Ground terminal
O Chip enable signal output to the serial fl ash
I Audio muting control signal input from the digital audio interface receiver or HDMI receiver
O Interrupt request signal output to the DSP controller
- Ground terminal
I PLL lock error signal and data error fl ag input from the DSP1
I Master clock signal input from the digital audio interface receiver or HDMI receiver
I/O Two-way data bus with S-RAM and address signal output to the address latch
- Power supply terminal (+1.2V)
- Power supply terminal (+3.3V)
Bit clock signal input for PCM audio signal input from the digital audio interface receiver,
I
DSP1 or HDMI receive
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I/O Two-way data bus with S-RAM and address signal output to the address latch
i
- Power supply terminal (+3.3V)
L/R sampling clock signal input for PCM audio signal input from the digital audio interface
I
receiver, DSP1 or HDMI receiver
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2 9
8
Description
Not used
Not used
Not used
Not used
Not used
Not used
Q Q
3 6 7 1 3 1 5
"L": reset
co
.
9 4 2 8
0 5 8 2 9 9 4 2 8
m
9 9
9 9