Sony STR-DN850 Service Manual page 98

STR-DN860/DN1060
Pin No. Pin Name
AE22 NFCEN2
AE23 NFD0
AE24 NFWEN
AE25 HTPLG_RX
AE26 PWR5V_RX2
TP_MEMPLL,
AF1, AF2
TN_MEMPLL
AF3 NC
AF4 RDQ25
AF5 DGND12_K
AF6 RDQ28
AF7 DDRVCCIO1
AF8, AF9 RDQ20, RDQ22
AF10 DDRVCCIO1
AF11, AF12 RA9, RA5
AF13 RCS_
AF14 to
RDQ3, RDQ1, RDQ9
AF16
AF17, AF18 DDRVCCIO1
AF20 RDQ5
AF21 NFD6
AF22 NFCEN
AF23 NFD1
AF24 NFALE
AF25 UARXD
AF26 RESET_
AF27 DDC_SDA_RX
AF28 DDC_SCL_RX
RDQ17, RDQ16,
AG1 to AG4
RDQ26, RDQ27
AG5 RDQS2
AG6 RCLK1
AG7 RDQS3_
AG8 RDQ21
AG10 RBA2
AG11,
RA2, RA11
AG13
AG14 RDQ0
AG16 RDQS0
AG17 RCLK0
AG18 RDQS1_
AG19,
RDQ7, RDQ4
AG20
AG21 to
NFD7, NFD4, NFD2
AG23
AG25 GPIO8
AG26 VCLK
AG27 VDATA
AG28 LCDRD
RDQ18, RDQ19,
AH1 to AH3
RDQ24
AH4 RDQM3
AH5 RDQS2_
AH6 RCLK1_
AH7 RDQS3
AH8 RDQ23
AH10,
RA0, RA7
AH11
98
I/O
- Not used
I/O Two-way data bus with the NAND fl ash
O Write enable signal output to the NAND fl ash
O Hot plug detection signal output to the HDMI IN 1 connector
I Power supply voltage (+5V) input from the HDMI IN 2 connector
- Not used
- Not used
I/O Two-way data bus with the SD-RAM
- Ground terminal
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.5V)
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.5V)
O Address signal output to the SD-RAM
O Chip select signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
- Power supply terminal (+1.5V)
I/O Two-way data bus with the SD-RAM
I/O Two-way data bus with the NAND fl ash
O Chip enable signal output to the NAND fl ash
I/O Two-way data bus with the NAND fl ash
O Address latch enable signal output to the NAND fl ash
- Not used
I Reset signal input from the system controller "L": reset
I/O Two-way I2C data bus with the HDMI IN 1 connector
O I2C clock signal output to the HDMI IN 1 connector
I/O Two-way data bus with the SD-RAM
O Data strobe signal (positive) output to the SD-RAM
O Clock signal (positive) output to the SD-RAM
O Data strobe signal (negative) output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Bank address signal output to the SD-RAM
O Address signal output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Data strobe signal (positive) output to the SD-RAM
O Clock signal (positive) output to the SD-RAM
O Data strobe signal (negative) output to the SD-RAM
I/O Two-way data bus with the SD-RAM
I/O Two-way data bus with the NAND fl ash
O VBUS on/off control signal output terminal for WLAN/BT COMBO card "H": VBUS on
O Serial data transfer clock signal output to the system controller
I Serial data input from the system controller
O Serial data output to the system controller
I/O Two-way data bus with the SD-RAM
O Data mask signal output to the SD-RAM
O Data strobe signal (negative) output to the SD-RAM
O Clock signal (negative) output to the SD-RAM
O Data strobe signal (positive) output to the SD-RAM
I/O Two-way data bus with the SD-RAM
O Address signal output to the SD-RAM
Description