Sony STR-DN850 Service Manual page 101

Pin No. Pin Name
E7 DML
E8 VSSQ
E9 VDDQ
F1 VDDQ
F2 DQL2
F3 DQSL
F4 NO_USE
F5 NO_USE
F6 NO_USE
F7 DQL1
F8 DQL3
F9 VSSQ
G1 VSSQ
G2 DQL6
G3 DQSL
G4 NO_USE
G5 NO_USE
G6 NO_USE
G7 VDD
G8 VSS
G9 VSSQ
H1 VREFDQ
H2 VDDQ
H3 DQL4
H4 NO_USE
H5 NO_USE
H6 NO_USE
H7 DQL7
H8 DQL5
H9 VDDQ
J1 NC
J2 VSS
J3 RAS
J4 NO_USE
J5 NO_USE
J6 NO_USE
J7 CK
J8 VSS
J9 NC
K1 ODT
K2 VDD
I/O
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM
is sampled HIGH coincident with that input data during a Write access. DM is sampled on
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both edges of DQS. For x8 device, the function of DM or TDQS/ TDQS is enabled by Mode
Register A11 setting in MR1.
-
DQ Ground
-
DQ Power Supply: 1.5V +/-0.075V
-
DQ Power Supply: 1.5V +/-0.075V
I/O
Data Input/output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
I/O
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
-
Not used
- Not used
-
Not used
I/O
Data Input/output: Bi-directional data bus.
I/O
Data Input/output: Bi-directional data bus.
-
DQ Ground
-
DQ Ground
I/O
Data Input/output: Bi-directional data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, cen-
tered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corre-
sponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with
I/O
differential signals DQS, DQSL and DQSU, respectively, to provide differential pair signaling
to the system during reads and writes. DDR3 SDRAM supports differential data strobe only
and does not support single-ended.
-
Not used
-
Not used
-
Not used
-
Power Supply: 1.5V +/-0.075
-
Ground
-
DQ Ground
-
Reference voltage for DQ
-
DQ Power Supply: 1.5V +/-0.075V
I/O
Data Input/output: Bi-directional data bus.
-
Not used
-
Not used
-
Not used
I/O
Data Input/output: Bi-directional data bus.
I/O
Data Input/output: Bi-directional data bus.
-
DQ Power Supply: 1.5V +/-0.075V
-
No Connect: No internal electrical connection is present.
-
Ground
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Command Input: RAS (along with CS) defi ne the command being entered.
-
Not used
-
Not used
-
Not used
Clock: CK is differential clock input. All address and control input signals are sampled on the
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crossing of the positive edge of CK. Output (read) data is referenced to the crossing of CK.
-
Ground
-
No Connect: No internal electrical connection is present.
On Die Termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS,
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NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 confi gura-
tions. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT.
-
Power Supply: 1.5V +/-0.075
STR-DN860/DN1060
Description
101