Sony STR-DN850 Service Manual page 104

STR-DN860/DN1060
MB-1409 BOARD (11/18)
Pin No. Pin Name
1 VCC
2 ADV8003_SPSF_DIN
ADV8003_SPSF_
3
DOUT
4 ADV8003_SPSF_SCK
ADV8003_P_
5
CONT_1.8V
6 ADV8003_RESET
7 ADV8003_SPI_CS
8 TEST1
9 TEST2
10 TEST3
11 TEST4
12 TEST5
13 ADV8003_INT0
14 ADV8003_INT1
15 ADV8003_INT2
16 ADV8003_P_DOWN
17 SWSEL_A
18 SWSEL_B
19 CEC_IN_OUT
20 E2P_SDA
21 E2P_SCL
22 HDMI_CECIN
23 HDMI_CECOUT
24 CEC_PCONT
25 TEST_6
26 TEST_7
27 VSS
28 TEST_8
29 BD_SCL(IF_SCK)
30 BD_SDI(IF_SDO)
31 BD_SDO(IF_SDI)
32 BD_CS(XIF_CS)
WOL_WLAN(WOL_
33
INT)
BD_IF_START(START_
34
BIT)
35 BD_REQ(SYS_REQ)
BD_RESET(CPU_
36
XRST)
JIG_MODE1(EXT_JIG_
37
MODE1)
38 OPWRSB
39 UPG_STATUS
PCONT_WOL_STAND-
40
BY
41 NAND_RESET
42 MTK_ZONE2_MUTE
43 MTK_ZONE2_RST
44 VSS
45 VCC
46 SIRCS_IN
47 HP_DET
48 NC
49 FL_ENABLE
50 FL_BK
104
IC3002 MB9BF129TPMC-GE1 (SYSTEM CONTROLLER)
I/O
- Power supply pin (+3.3V)
I ADV8003 SPI SOMI
O ADV8003 SPI SIMO
O ADV8003 SPI SCK
O HDMI ADV 18V CONT
O ADV8003 RESET signal output terminal
O ADV8003 Chip Select
O Test Pad 1 (for designer evaluation only)
O Test Pad 2 (for designer evaluation only)
O Test Pad 3 (for designer evaluation only)
O Test Pad 4 (for designer evaluation only)
O Test Pad 5 (for designer evaluation only)
I ADV8003 INTerrupt port 0
I ADV8003 INTerrupt port 1
I ADV8003 INTerrupt port 2
O ADV8003 POWER DOWN
O HDMI Switcher 5V Power Select
O HDMI Switcher 5V Power Select
I/O CEC Input/Output Peripheral
I/O Two-way data bus with the EEPROM
O Serial data transfer clock signal output to the EEPROM
- CEC Serial data input from the HDMI connector (Not Used)
- CEC serial data output to the HDMI connector (No Used)
O Control the CEC relay at HDMI out terminal.
O Test Pad 6 (for designer evaluation only)
O Test Pad 7 (for designer evaluation only)
- Ground terminal
O Test Pad 8 (for designer evaluation only)
I Serial data transfer clock signal input from MT8506
O Serial data output to MT8506
I Serial data input from MT8506
O Chip select signal output to MT8506
I WOL (wake-on-LAN) wake-up signal input from MT8506 "H":wake-up
O Ready signal output to MT8506 "H":ready
I Request signal input from MT8506 "H": request
O Reset signal output to MT8506 "L": reset
This port is Jig mode selection signal OUTPUT to MT8506.
I/O
(Normal case this port is input. Output LOW when USB update start by FLD. )
I Power control signal input from the BD decoder
I UPG signal input from MT8506
O Wake On Lan Power Control
O Reset signal output to the NAND fl ash "L": reset
O MTK ZONE2 DAC MUTE
O MTK ZONE2 DAC RESET
- Ground Terminal
- Power supply pin (+3.3V)
I SIRCS signal input
I Headphone Detection signal input
- Not used
O Enable control for FL DISPLAY DRIVER IC
O Blanking period signal output to the fl uorescent indicator tube
Description