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AGP Fast Write (Disabled)
This item lets you enable or disable the caching of display data for the video
memory of the processor. Enabling this item can greatly improve the display
speed. Disable this item if your graphics display card does not support this
feature.
AGP Master 1 WS Write (Disabled)
This implements a single delay when writing to the AGP Bus. By default, two-
wait states are used by the system, providing greater stability.
AGP Master 1 WS Read (Disabled)
This implements a single delay when reading to the AGP Bus. By default, two-
wait states are used by the system, allowing for greater stability.
DBI Output for AGP Trans. (Disabled)
This item is use to improve the signal quality for the AGP 3.0.
Press <Esc> to return to the Advanced Chipset Features screen.
CPU & PCI Bus Control
Scroll to this item and press <Enter> to view the following screen:
Phoenix – AwardBIOS CMOS Setup Utility
CPU to PCI Write Buffer
PCI Master 0 WS Write
PCI Delay Transaction
↑ ↓ → ← : Move Enter: Select
F5:Previous Values
CPU to PCI Write Buffer (Enabled)
When enabled, writes from the CPU to PCI bus is buffered, to compensate for
the speed differences between the CPU and PCI bus. When disabled, the
writes are not buffered and the CPU must wait until the write is complete
before starting another write cycle.
PCI Master 0 WS Write (Enabled)
When enabled, writes to the PCI bus are executed with zero wait states.
PCI Delay Transaction (Disabled)
The mainboard's chipset has an embedded 32-bit post write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1.
Press <Esc> to return to the Advanced Chipset Features screen.
CPU & PCI Bridge Control
[Enabled]
[Enabled]
[Disabled]
+/-/PU/PD: Value:
F10: Save ESC: Exit
F6:Fail-Safe Defaults
36
Item Help
Menu Level
F1:General Help
F7:Optimized Defaults
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