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J5
Detail:
Default
is open
J1
Detail:
Hard-wired
Default Position
J4
Detail:
Default Position
4.0 Functional Description
The ADC08100 Evaluation Board schematic is shown in
Figure 2.
4.1 Input (signal conditioning) circuitry
The input signal to be digitized should be applied to BNC
connector J2. This 50 Ohm input is intended to accept a
low-noise sine wave signal of 1.5V peak-to-peak
amplitude. To accurately evaluate the ADC08100
dynamic performance, the input test signal should be
passed through a high-quality bandpass filter (60dB
minimum stop-band attenuation) as even the best
generators do not provide a pure enough sine wave to
properly evaluate an ADC.
Resistors R15, R15A, R16 and R18 provide the needed
input bias to the ADC08100. You can center the input
signal to the ADC by adjusting reference voltages V RT
and V RB with VR1 and VR2 or by making slight
adjustments to voltage an Power Connector pin 1.
J4
J1
CLK_SEL
NUM_MEM
DL0
DL1
DIV_EN
J5
U5
J1
NUM_MEM
TP5
U8
U7
DGND
HP1
HP2
J4
CLK_SEL
Y1
Q3
T1
TP2
Q4
VRT
Q5
INPUT
TP3
TP7
D4
AGND
NATIONAL SEMICONDUCTOR
J2
INPUT
ADC08100/ADC08200 EVAL BOARD
TP7
TP2
INPUT
VRT
INPUT BNC
Figure 1. Component and Test Point Locations
TP1
TP9
PD
+3V
J3
U3
U2
Socket
TP8
DGND
TP9
+3V
TP1
PD
U1
L1
L3
U6
POWER CONNECTOR
L2
TP4
VRB
Q1
Q2
L4
TP3
AGND
U4
VR1
VR2
J2
VR1
VR2
VRB ADJ
VRT ADJ
4.2 ADC reference circuitry
The provided reference circuitry will provide nominal
reference voltage ranges of 1.3V to 2.6V for V RT and 0V
to 1.3V for V RB , Providing for nominal input ranges of 0V
to 2.6V peak-to-peak. Note that this is beyond the
maximum specified 2.3V range of the ADC08100.
The reference voltages for the ADC08100 can be
monitored at test points TP2 and TP4 and are set with
VR1 and VR2. Signal offset can be provided by adjusting
both of these potentiometers, or by minor adjustments to
the +5 Volts at pin 1 of Power Connector P1.
4.3 ADC clock circuit
The clock signal applied to the ADC is selected with
jumper J4. A standard ECL-level 100 MHz crystal
oscillator should be installed at Y1 and the divide by 2
function selected by shorting pins 1 and 2 of jumper JP4.
6
P1
+5V
GND
+5V
-5.2V
TP4
VRB
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