Texas Instruments Technology for Innovators 4Q 2006 Manual page 17

UARTs (Universal Asynchronous Receiver/Transmitters)
UART Selection Guide
Device Channel(s) FIFOs
Universal Asynchronous Receiver/Transmitters (UARTs)
TL16C2550 2 16-Byte
TL16C2552 2 16-Byte
TL16C2752 2 64-Byte
TL16C450 1 None
TL16C451 1 None
TL16C452 2 None
TL16C550C 1 16-Byte
TL16C550D 1 16-Byte
TL16C552A 2 16-Byte
TL16C554A 4 16-Byte
TL16C750 1 16/64-Byte
TL16C752B 2 64-Byte
TL16C754B 4 64-Byte
TL16PC564B/BLV 1 16/64-Byte
TL16PIR552 2 16-Byte
*Suggested resale price in U.S. dollars in quantities of 1,000.
TL16C550D Asynchronous Communications Element
Get samples, datasheets, EVMs and reports at:
Asynchronous Communications Element
with Autoflow Control
The TL16C550D is a performance-enhanced
version of TI's industry-standard TL16C550C
single-channel UART with 16-byte FIFO. The
TL16C550D can support voltages of down to
2.5 V and data transfer rates of up to 1.5
Mbps. Combining these features with an
ultra-small 32-pin QFN package, the
TL16C550D is ideal for a variety of portable
applications.
Key Features
• Expanded voltage and package options
ideal for small form factors
• Lower voltage and higher frequency than
TL16C550C
• Pin-for-pin replacement for TL16C550C
• Programmable auto-RTS and auto-CTS
(autoflow)
Texas Instruments 4Q 2006
Voltage Characterized
(V) Temp. (°C) Package(s)
1.8/2.5/3.3/5 –40 to 85 32 QFN, 44 PLCC,
1.8/2.5/3.3/5 –40 to 85 32 QFN, 44 PLCC
1.8/2.5/3.3/5 —
5 0 to 70 40 DIP, 44 PLCC
5 0 to 70
5 0 to 70
3.3/5 –40 to 85 40 DIP, 44 PLCC,
48 LQFP, 48 TQFP
2.5/3.3/5 –40 to 85
48 LQFP, 48 TQFP
5 –40 to 85 68 PLCC, 80 TQFP
5 –40 to 85 68 PLCC, 80 LQFP
5 –40 to 85 44 PLCC, 64 LQFP
3.3 –40 to 85 48 LQFP, 48 TQFP
3.3/5 –40 to 85 68 PLCC, 80 LQFP
3.3/5 0 to 70 100 BGA, 100 LQFP
5 0 to 70
www.ti.com/sc/device/TL16C550D
• Up to 24/20/16-MHz clock rates for
up to 1.5/1.25/1-Mbps operation
• Programmable baud-rate generator
allows division to generate internal
16x clock
• Independent clock input receiver
• Fully programmable serial interface
characteristics
• Available packages: DIP, PLCC,
TQFP and QFN
Applications
• PDAs
• MP3 players
• Gaming systems
• Modems
• Serial ports
• Telecom
Dual UART with Programmable Auto-RTS and Auto-CTS
48 TQFP
Dual UART with Programmable Auto-RTS and Auto-CTS
44 PLCC Dual UART with Customizable Trigger Levels
68 PLCC Single UART with Parallel Port
68 PLCC Dual UART with Parallel Port
Single UART with Hardware Autoflow Control
32 QFN Single UART with Hardware Autoflow Control
Dual UART with Parallel Port
Quad UART with Hardware Autoflow Control
Single UART with Hardware Autoflow Control, Low-Power Modes
Dual UART with Hardware Autoflow Control, Low-Power Modes
Dual UART with Hardware Autoflow Control, Low-Power Modes
Single UART with PCMCIA Interface
80 QFP Dual UART with Selectable IR & 1284 Modes
Functional block diagram ( for PT and PFB packages)
Internal
Data Bus
4–2
47–43 Data
D(7–0)
Bus
Buffer
28
A0
27
A1
26
A2
9
CS0
10
CS1
11
CS2
24
ADS
35 Select
MR
and
19
Control
RD1
Logic
20
RD2
16
WR1
17
WR2
22
DDIS
23
TXRDY
14
XIN
15
XOUT
29
RXRDY
42
V
CC
Power
18
V Supply
SS
Functional block diagram.
Description
Single UART
S
e
l Receiver
8
e FIFO
8
c
t
Receiver
Receiver Shift
Buffer Register
Register
Receiver
Line
Timing and
Control
Control
Register
Divisor
Latch (LS)
Baud
Generator
Divisor
Latch (MS)
Transmitter
Line
Timing and
Status
Control
Register
S
Transmitter
e
FIFO
l
e
Transmitter
Transmitter 8 8
c
Shift
Holding
t
Register
Register
Modem
8
Control
Register
Modem
Modem
8
Control
Status
Register Logic
Interrupt Interrupt
8
Enable Control
Register Logic
Interrupt
8
Identification
Register
FIFO
Control
Register
Interface Selection Guide
17
Price *
2.80
3.00
Call
1.50
2.50
2.55
1.75
1.75
3.85
6.00
3.70
3.10
8.35
5.90/6.10
6.10
7
SIN
5
RCLK
32
RTS
12
BAUDOUT
Autoflow
Control
(AFE)
8
SOUT
38
CTS
33
DTR
39
DSR
40
DCD
41
RI
34
OUT1
31
OUT2
30
INTRPT