Sharp MZ-80B Owner's Manual page 117
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- Owner's manual (138 pages) ,
- Reference manual (94 pages) ,
- Service manual (83 pages)
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108
A.2
Technical
Data of ZSOA-PIO
1.0 INTRODUCTION
The Z-80A Parallel 1/0 (PIO) Circuit is a programmable, two port device which provides a TTL compatible inter-
face
between peripheral devices and the Z-80A-CPU. The CPU
can configure
the Z-80A-PIO to interface with
a
wide
range
of
peripheral devices with no
other
external logic required. Typical peripheral devices that
are
fully
compatible
with the Z-80A-PIO include most keyboards, paper tape readers
and
punches, printers, PROM programmers, etc. The
Z-80A-PIO utilizes N channel silicon gate depletion load technology and is packaged in a 40 pin DIP. Major features of
the Z-80A-PIO include:
• Two independent 8 bit bidirectional peripheral interface ports with
'handshake'
data transfer control
• Interrupt driven 'handshake' for fast response
• Any one of four distinct modes
of
operation may be selected
for
a port including:
Byte
output
Byte input
Byte bidirectional bus (Available on Port A only)
Bit control mode
All
with
interrupt controlled handshake
• Daisy chain priority interrupt logic included to provide
for automatic
interrupt vectoring
without
external logic
•
Eight outputs
are
capable of driving Darlington transistors
• All inputs and outputs fully TTL compatible
• Single
5
volt supply and
single
phase clock are required.
One of the unique
features of
the Z-80A-PIO that separates
it
from other interface controllers is that
all
data
transfer between the peripheral device
and
the CPU is accomplished under total
interrupt
control. The interrupt logic of
the PIO permits
full
usage of the efficient interrupt
capabilities of
the Z-80A-CPU during 1/0 transfers. All logic neces-
sary
to implement a
fully
nested interrupt structure is included
in
the PIO so that
additional
circuits are not required.
Another unique feature of the PIO is that
it
can
be programmed to interrupt
the
CPU on the
occurrence
of
specified
status conditions in the peripheral device. For example, the PIO
can
be programmed to interrupt if any
specified
peri-
pheral alarm conditions should occur. This interrupt capability reduces the amount of time that the processor must
spend in polling peripheral status.
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